@@ -1289,8 +1289,6 @@ static int ac97_initfn (PCIDevice *dev)
c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
- c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
-
/* TODO set when bar is registered. no need to override. */
/* nabmar native audio mixer base address rw */
c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
@@ -319,7 +319,6 @@ static int piix4_pm_initfn(PCIDevice *dev)
pci_conf = s->dev.config;
pci_conf[0x06] = 0x80;
pci_conf[0x07] = 0x02;
- pci_conf[0x09] = 0x00;
pci_conf[0x3d] = 0x01; // interrupt pin 1
pci_conf[0x40] = 0x01; /* PM io base read only bit */
@@ -690,9 +690,6 @@ static int bonito_initfn(PCIDevice *dev)
{
PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
- /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
- pci_config_set_prog_interface(dev->config, 0x00);
-
/* set the north bridge register mapping */
s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s,
DEVICE_NATIVE_ENDIAN);
@@ -104,7 +104,6 @@ static int pci_grackle_init_device(SysBusDevice *dev)
static int grackle_pci_host_init(PCIDevice *d)
{
- d->config[0x09] = 0x01;
return 0;
}
@@ -115,6 +114,7 @@ static PCIDeviceInfo grackle_pci_host_info = {
.vendor_id = PCI_VENDOR_ID_MOTOROLA,
.device_id = PCI_DEVICE_ID_MOTOROLA_MPC106,
.revision = 0x00, // revision
+ .prog_interface = 0x01,
.class_id = PCI_CLASS_BRIDGE_HOST,
};
@@ -1121,7 +1121,6 @@ static int gt64120_pci_init(PCIDevice *d)
pci_set_word(d->config + PCI_COMMAND, 0);
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
- pci_config_set_prog_interface(d->config, 0);
pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
@@ -226,8 +226,6 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
qemu_irq *irq;
int i;
- pci_conf[PCI_CLASS_PROG] = 0x8f;
-
pci_conf[0x51] = 0x04; // enable IDE0
if (d->secondary) {
/* XXX: if not enabled, really disable the seconday IDE controller */
@@ -279,6 +277,7 @@ static PCIDeviceInfo cmd646_ide_info[] = {
.vendor_id = PCI_VENDOR_ID_CMD,
.device_id = PCI_DEVICE_ID_CMD_646,
.revision = 0x07, // IDE controller revision
+ .prog_intarface = 0x8f,
.class_id = PCI_CLASS_STORAGE_IDE,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
@@ -77,8 +77,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
struct AHCIPCIState *d;
d = DO_UPCAST(struct AHCIPCIState, card, dev);
- pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);
-
d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
d->card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
pci_config_set_interrupt_pin(d->card.config, 1);
@@ -129,6 +127,7 @@ static PCIDeviceInfo ich_ahci_info[] = {
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82801IR,
.revision = 0x02,
+ .prog_interface = AHCI_PROGMODE_MAJOR_REV_1,
.class_id = PCI_CLASS_STORAGE_SATA,
},{
/* end of list */
@@ -134,9 +134,6 @@ static void pci_piix_init_ports(PCIIDEState *d) {
static int pci_piix_ide_initfn(PCIDevice *dev)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
- uint8_t *pci_conf = d->dev.config;
-
- pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
qemu_register_reset(piix3_reset, d);
@@ -180,6 +177,7 @@ static PCIDeviceInfo piix_ide_info[] = {
.init = pci_piix_ide_initfn,
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82371SB_1,
+ .prog_interface = 0x80, // legacy ATA mode
.class_id = PCI_CLASS_STORAGE_IDE,
},{
.qdev.name = "piix4-ide",
@@ -189,6 +187,7 @@ static PCIDeviceInfo piix_ide_info[] = {
.init = pci_piix_ide_initfn,
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82371AB,
+ .prog_interface = 0x80, // legacy ATA mode
.class_id = PCI_CLASS_STORAGE_IDE,
},{
/* end of list */
@@ -160,7 +160,6 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);;
uint8_t *pci_conf = d->dev.config;
- pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
qemu_register_reset(via_reset, d);
@@ -190,6 +189,7 @@ static PCIDeviceInfo via_ide_info = {
.vendor_id = PCI_VENDOR_ID_VIA,
.device_id = PCI_DEVICE_ID_VIA_IDE,
.revision = 0x06, /* Revision 0.6 */
+ .prog_interface = 0x8a, /* legacy ATA mode */
.class_id = PCI_CLASS_STORAGE_IDE,
};
@@ -754,6 +754,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
pci_config_set_vendor_id(pci_dev->config, info->vendor_id);
pci_config_set_device_id(pci_dev->config, info->device_id);
pci_config_set_revision(pci_dev->config, info->revision);
+ pci_config_set_prog_interface(pci_dev->config, info->prog_interface);
pci_config_set_class(pci_dev->config, info->class_id);
if (!info->is_bridge) {
@@ -436,6 +436,7 @@ typedef struct {
uint16_t vendor_id;
uint16_t device_id;
uint8_t revision;
+ uint8_t prog_interface;
uint16_t class_id;
uint16_t subsystem_vendor_id; /* only for header type = 0 */
uint16_t subsystem_id; /* only for header type = 0 */
@@ -557,7 +557,6 @@ pci_ebus_init1(PCIDevice *s)
s->config[0x05] = 0x00;
s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
s->config[0x07] = 0x03; // status = medium devsel
- s->config[0x09] = 0x00; // programming i/f
s->config[0x0D] = 0x0a; // latency_timer
pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY,
@@ -1716,7 +1716,6 @@ static int usb_ohci_initfn_pci(struct PCIDevice *dev)
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
int num_ports = 3;
- ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
/* TODO: RST# value should be 0. */
ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
@@ -1758,6 +1757,7 @@ static PCIDeviceInfo ohci_pci_info = {
.init = usb_ohci_initfn_pci,
.vendor_id = PCI_VENDOR_ID_APPLE,
.device_id = PCI_DEVICE_ID_APPLE_IPID_USB,
+ .prog_interface = 0x10, /* OHCI */
.class_id = PCI_CLASS_SERIAL_USB,
};
@@ -1121,7 +1121,6 @@ static int usb_uhci_common_initfn(PCIDevice *dev)
uint8_t *pci_conf = s->dev.config;
int i;
- pci_conf[PCI_CLASS_PROG] = 0x00;
/* TODO: reset value should be 0. */
pci_conf[PCI_INTERRUPT_PIN] = 4; // interrupt pin 3
pci_conf[0x60] = 0x10; // release number
@@ -486,15 +486,11 @@ static const VMStateDescription vmstate_via = {
/* init the PCI-to-ISA bridge */
static int vt82c686b_initfn(PCIDevice *d)
{
- uint8_t *pci_conf;
uint8_t *wmask;
int i;
isa_bus_new(&d->qdev);
- pci_conf = d->config;
- pci_config_set_prog_interface(pci_conf, 0x0);
-
wmask = d->wmask;
for (i = 0x00; i < 0xff; i++) {
if (i<=0x03 || (i>=0x08 && i<=0x3f)) {