From patchwork Wed Sep 9 15:41:58 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?5q2m55SwID0/SVNPLTIwMjItSlA/Qj9JQnNrUWoxVFRHa2JLRUk9Pz0=?= X-Patchwork-Id: 33205 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by bilbo.ozlabs.org (Postfix) with ESMTPS id D4729B6F20 for ; Thu, 10 Sep 2009 02:18:37 +1000 (EST) Received: from localhost ([127.0.0.1]:53388 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MlPsP-0001VK-2A for incoming@patchwork.ozlabs.org; Wed, 09 Sep 2009 12:18:33 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MlPJD-0008Ex-8p for qemu-devel@nongnu.org; Wed, 09 Sep 2009 11:42:11 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MlPJ8-0008Cz-SI for qemu-devel@nongnu.org; Wed, 09 Sep 2009 11:42:10 -0400 Received: from [199.232.76.173] (port=58216 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MlPJ8-0008Cp-IZ for qemu-devel@nongnu.org; Wed, 09 Sep 2009 11:42:06 -0400 Received: from smtp-vip.mem.interq.net ([210.157.1.50]:21851 helo=smtp02.mem.internal-gmo) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MlPJ7-0007Zu-Rc for qemu-devel@nongnu.org; Wed, 09 Sep 2009 11:42:06 -0400 Received: (from root@localhost) by smtp02.mem.internal-gmo (8.13.8/8.12.6) id n89Fg4Pi026293 for qemu-devel@nongnu.org; Thu, 10 Sep 2009 00:42:04 +0900 (JST) Received: from YOUR-BD18D6DD63.m1.interq.or.jp (ntymns034018.ymns.nt.ftth.ppp.infoweb.ne.jp [211.2.27.18]) by smtp02.mem.internal-gmo with ESMTP id n89Fg4S2026288 for ; (me101664 for with PLAIN) Thu, 10 Sep 2009 00:42:04 +0900 (JST) Message-Id: <200909091541.AA00088@YOUR-BD18D6DD63.m1.interq.or.jp> From: t-takeda@m1.interq.or.jp (=?ISO-2022-JP?B?GyRCSXBFRBsoQg==?= =?ISO-2022-JP?B?IBskQj1TTGkbKEI=?=) Date: Thu, 10 Sep 2009 00:41:58 +0900 To: qemu-devel MIME-Version: 1.0 X-Mailer: AL-Mail32 Version 1.13 X-detected-operating-system: by monty-python.gnu.org: Solaris 10 (beta) Subject: [Qemu-devel] [PATCH 05/14] dma: support NEC PC-9821 family X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch is to add NEC PC-9821 family i/o to dma. diff -ur a/hw/dma.c b/hw/dma.c --- a/hw/dma.c Tue Sep 8 21:26:50 2009 +++ b/hw/dma.c Wed Sep 9 21:51:15 2009 @@ -41,6 +41,7 @@ uint8_t mode; uint8_t page; uint8_t pageh; + uint8_t bound; uint8_t dack; uint8_t eop; DMA_transfer_handler transfer_handler; @@ -55,8 +56,11 @@ uint8_t command; uint8_t mask; uint8_t flip_flop; + uint8_t access_ctrl; int dshift; struct dma_regs regs[4]; + /* NEC PC-98x1 quirks? */ + int pc98; } dma_controllers[2]; enum { @@ -329,7 +333,8 @@ static void channel_run (int ncont, int ichan) { int n; - struct dma_regs *r = &dma_controllers[ncont].regs[ichan]; + struct dma_cont *d = &dma_controllers[ncont]; + struct dma_regs *r = &d->regs[ichan]; #ifdef DEBUG_DMA int dir, opmode; @@ -344,11 +349,26 @@ } #endif - r = dma_controllers[ncont].regs + ichan; n = r->transfer_handler (r->opaque, ichan + (ncont << 2), r->now[COUNT], (r->base[COUNT] + 1) << ncont); r->now[COUNT] = n; ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); + + /* increment page register */ + if (d->pc98 && r->bound) { + uint32_t last_addr = r->base[ADDR]; + if ((r->mode >> 5) & 1) { + last_addr -= n >> ncont; + if (last_addr & 0xffff0000) { + r->page = ((r->page - 1) & r->bound) | (r->page & (~r->bound)); + } + } else { + last_addr += n >> ncont; + if (last_addr & 0xffff0000) { + r->page = ((r->page + 1) & r->bound) | (r->page & (~r->bound)); + } + } + } } static QEMUBH *dma_bh; @@ -400,9 +420,13 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len) { - struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; + struct dma_cont *d = &dma_controllers[nchan > 3]; + struct dma_regs *r = &d->regs[nchan & 3]; target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; + if (d->pc98 && (d->access_ctrl & 4)) { + addr &= 0xfffff; + } if (r->mode & 0x20) { int i; uint8_t *p = buf; @@ -422,9 +446,13 @@ int DMA_write_memory (int nchan, void *buf, int pos, int len) { - struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; + struct dma_cont *d = &dma_controllers[nchan > 3]; + struct dma_regs *r = &d->regs[nchan & 3]; target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; + if (d->pc98 && (d->access_ctrl & 4)) { + addr &= 0xfffff; + } if (r->mode & 0x20) { int i; uint8_t *p = buf; @@ -453,6 +481,14 @@ static void dma_reset(void *opaque) { struct dma_cont *d = opaque; + + if (d->pc98) { + int i; + for (i = 0; i < ARRAY_SIZE (d->regs); ++i) { + d->regs[i].bound = 0; + } + d->access_ctrl = 0xb4; + } write_cont (d, (0x0d << d->dshift), 0); } @@ -470,6 +506,7 @@ static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; int i; + d->pc98 = 0; d->dshift = dshift; for (i = 0; i < 8; i++) { register_ioport_write (base + (i << dshift), 1, 1, write_chan, d); @@ -509,6 +546,9 @@ qemu_put_8s (f, &d->command); qemu_put_8s (f, &d->mask); qemu_put_8s (f, &d->flip_flop); + if (d->pc98) { + qemu_put_8s (f, &d->access_ctrl); + } qemu_put_be32 (f, d->dshift); for (i = 0; i < 4; ++i) { @@ -520,6 +560,9 @@ qemu_put_8s (f, &r->mode); qemu_put_8s (f, &r->page); qemu_put_8s (f, &r->pageh); + if (d->pc98) { + qemu_put_8s (f, &r->bound); + } qemu_put_8s (f, &r->dack); qemu_put_8s (f, &r->eop); } @@ -537,6 +580,9 @@ qemu_get_8s (f, &d->command); qemu_get_8s (f, &d->mask); qemu_get_8s (f, &d->flip_flop); + if (d->pc98) { + qemu_get_8s (f, &d->access_ctrl); + } d->dshift=qemu_get_be32 (f); for (i = 0; i < 4; ++i) { @@ -548,6 +594,9 @@ qemu_get_8s (f, &r->mode); qemu_get_8s (f, &r->page); qemu_get_8s (f, &r->pageh); + if (d->pc98) { + qemu_get_8s (f, &r->bound); + } qemu_get_8s (f, &r->dack); qemu_get_8s (f, &r->eop); } @@ -565,6 +614,106 @@ high_page_enable ? 0x488 : -1); register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]); register_savevm ("dma", 1, 1, dma_save, dma_load, &dma_controllers[1]); + + dma_bh = qemu_bh_new(DMA_run_bh, NULL); +} + +/* NEC PC-98x1 */ + +static const uint8_t bounds[4] = {0, 0x0f, 0, 0xff}; + +static void pc98_write_chan(void *opaque, uint32_t nport, uint32_t data) +{ + write_chan (opaque, nport >> 1, data); +} + +static uint32_t pc98_read_chan(void *opaque, uint32_t nport) +{ + return read_chan (opaque, nport >> 1); +} + +static void pc98_write_cont (void *opaque, uint32_t nport, uint32_t data) +{ + write_cont (opaque, nport >> 1, data); +} + +static uint32_t pc98_read_cont (void *opaque, uint32_t nport) +{ + return read_cont (opaque, nport >> 1); +} + +static void pc98_write_page (void *opaque, uint32_t nport, uint32_t data) +{ + struct dma_cont *d = opaque; + int ichan; + + ichan = ((nport >> 1) + 1) & 3; + d->regs[ichan].page = data; +} + +static void pc98_write_bound (void *opaque, uint32_t nport, uint32_t data) +{ + struct dma_cont *d = opaque; + int ichan; + + ichan = data & 3; + d->regs[ichan].bound = bounds[(data >> 2) & 3]; +} + +static void pc98_write_access_ctrl (void *opaque, uint32_t nport, uint32_t data) +{ + struct dma_cont *d = opaque; + + d->access_ctrl = data; +} + +static uint32_t pc98_read_access_ctrl (void *opaque, uint32_t nport) +{ + struct dma_cont *d = opaque; + + return d->access_ctrl; +} + +static void pc98_write_pageh (void *opaque, uint32_t nport, uint32_t data) +{ + struct dma_cont *d = opaque; + int ichan; + + ichan = ((nport >> 1) - 2) & 3; + d->regs[ichan].pageh = data; +} + +void pc98_DMA_init (int high_page_enable) +{ + struct dma_cont *d = &dma_controllers[0]; + int i; + + d->pc98 = 1; + d->dshift = 0; + for (i = 0; i < 8; i++) { + register_ioport_write (0x01 + (i << 1), 1, 1, pc98_write_chan, d); + register_ioport_read (0x01 + (i << 1), 1, 1, pc98_read_chan, d); + register_ioport_write (0x11 + (i << 1), 1, 1, pc98_write_cont, d); + register_ioport_read (0x11 + (i << 1), 1, 1, pc98_read_cont, d); + } + for (i = 0; i < 4; i++) { + register_ioport_write (0x21 + (i << 1), 1, 1, pc98_write_page, d); + } + register_ioport_write (0x29, 1, 1, pc98_write_bound, d); + register_ioport_write (0x439, 1, 1, pc98_write_access_ctrl, d); + register_ioport_read (0x439, 1, 1, pc98_read_access_ctrl, d); + if (high_page_enable) { + /* mem > 16mb */ + for (i = 0; i < 4; i++) { + register_ioport_write (0xe05 + (i << 1), 1, 1, pc98_write_pageh, d); + } + } + qemu_register_reset(dma_reset, d); + dma_reset(d); + for (i = 0; i < ARRAY_SIZE (d->regs); ++i) { + d->regs[i].transfer_handler = dma_phony_handler; + } + register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]); dma_bh = qemu_bh_new(DMA_run_bh, NULL); }