From patchwork Tue Jun 24 01:11:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 363275 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 122671400BE for ; Tue, 24 Jun 2014 11:12:41 +1000 (EST) Received: from localhost ([::1]:56905 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzFHr-000700-67 for incoming@patchwork.ozlabs.org; Mon, 23 Jun 2014 21:12:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43837) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzFHD-00063g-F8 for qemu-devel@nongnu.org; Mon, 23 Jun 2014 21:12:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WzFH7-0004mb-FS for qemu-devel@nongnu.org; Mon, 23 Jun 2014 21:11:59 -0400 Received: from mail-yk0-x22e.google.com ([2607:f8b0:4002:c07::22e]:56525) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzFH7-0004m3-Aq for qemu-devel@nongnu.org; Mon, 23 Jun 2014 21:11:53 -0400 Received: by mail-yk0-f174.google.com with SMTP id 19so5195472ykq.33 for ; Mon, 23 Jun 2014 18:11:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=bF6u0GP9OyNWCXQabKTXpgNHdZDMwTnuZ7OL4II33Ws=; b=Mb6ozvcNXdM97IMLldytXld4n6PptbqXOL7r5N2oOC4OcQyOVK57LCiuGvZ18TEn0Y cHdtPCIMs2GCR3FYZ/DxqzJXhqtTEIO47IRfH5XMurw5vgvkBInm0nfn7jqOjU0ngydS ed5yhvqM8Q9z74OFQa/OLeuo4C8YmjSeLyoatshTaUKOQf8RCkcxKJsEyq8uIB0y4fS1 wkcuSbUMpInyaEXHdsmRcYDkvkHjiEkk9iuqD0XWCOMr+8vVPPk7o4r91De3AQKfZTLS xvEzBmBX/lqFGk0XzKrGlYKKdSDKaUxdfpCva5RlWf/a/oId/7fEVEv2kA9p2o2CE7cE uHdA== X-Received: by 10.236.170.194 with SMTP id p42mr41591361yhl.103.1403572312842; Mon, 23 Jun 2014 18:11:52 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id g25sm6276189yhc.25.2014.06.23.18.11.49 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 23 Jun 2014 18:11:52 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Date: Tue, 24 Jun 2014 11:11:47 +1000 Message-Id: <1f7986b24570943fd9d5a1d957ef64b5b3cba39e.1403572003.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4002:c07::22e Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, alistair.francis@xilinx.com Subject: [Qemu-devel] [PATCH v1 1/7] target-arm: Make the ARM PMCCNTR register 64-bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This makes the PMCCNTR register 64-bit to allow for the 64-bit ARMv8 version Signed-off-by: Peter Crosthwaite Signed-off-by: Alistair Francis --- target-arm/cpu.h | 2 +- target-arm/helper.c | 19 +++++++++---------- 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 369d472..cd1c7b6 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -223,7 +223,7 @@ typedef struct CPUARMState { /* If the counter is enabled, this stores the last time the counter * was reset. Otherwise it stores the counter value */ - uint32_t c15_ccnt; + uint64_t c15_ccnt; } cp15; struct { diff --git a/target-arm/helper.c b/target-arm/helper.c index ed4d2bb..ac10564 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -550,11 +550,10 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Don't computer the number of ticks in user mode */ - uint32_t temp_ticks; + uint64_t temp_ticks; - temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * - get_ticks_per_sec() / 1000000; + temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), + get_ticks_per_sec(), 1000000); if (env->cp15.c9_pmcr & PMCRE) { /* If the counter is enabled */ @@ -586,15 +585,15 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - uint32_t total_ticks; + uint64_t total_ticks; if (!(env->cp15.c9_pmcr & PMCRE)) { /* Counter is disabled, do not change value */ return env->cp15.c15_ccnt; } - total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * - get_ticks_per_sec() / 1000000; + total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), + get_ticks_per_sec(), 1000000); if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ @@ -606,7 +605,7 @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - uint32_t total_ticks; + uint64_t total_ticks; if (!(env->cp15.c9_pmcr & PMCRE)) { /* Counter is disabled, set the absolute value */ @@ -614,8 +613,8 @@ static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } - total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * - get_ticks_per_sec() / 1000000; + total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), + get_ticks_per_sec(), 1000000); if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */