| Message ID | 1626975764-22131-6-git-send-email-pmorel@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | s390x: CPU Topology | expand |
On 22/07/2021 19.42, Pierre Morel wrote: > The handling of STSI is enhenced with the interception of the s/enhenced/enhanced/ > function code 15 for storing CPU topology. > > Using the objects built during the pluging of CPU, we build the > SYSIB 15_1_x structures. > > With this patch the maximum MNEST level is 2, this is also > the only level allowed and only SYSIB 15_1_2 will be built. > > Signed-off-by: Pierre Morel <pmorel@linux.ibm.com> > --- > target/s390x/kvm/kvm.c | 101 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 101 insertions(+) > > diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c > index 9a0c13d4ac..0194756e6a 100644 > --- a/target/s390x/kvm/kvm.c > +++ b/target/s390x/kvm/kvm.c > @@ -52,6 +52,7 @@ > #include "hw/s390x/s390-virtio-ccw.h" > #include "hw/s390x/s390-virtio-hcall.h" > #include "hw/s390x/pv.h" > +#include "hw/s390x/cpu-topology.h" > > #ifndef DEBUG_KVM > #define DEBUG_KVM 0 > @@ -1907,6 +1908,102 @@ static void insert_stsi_3_2_2(S390CPU *cpu, __u64 addr, uint8_t ar) > } > } > > +static int stsi_15_container(void *p, int nl, int id) > +{ > + SysIBTl_container *tle = (SysIBTl_container *)p; > + > + tle->nl = nl; > + tle->id = id; > + > + return sizeof(*tle); > +} > + > +static int stsi_15_cpus(void *p, S390TopologyCores *cd) > +{ > + SysIBTl_cpu *tle = (SysIBTl_cpu *)p; > + > + tle->nl = 0; > + tle->dedicated = cd->dedicated; > + tle->polarity = cd->polarity; > + tle->type = cd->cputype; > + tle->origin = cd->origin; > + tle->mask = cd->mask; > + > + return sizeof(*tle); > +} > + > +static int set_socket(const MachineState *ms, void *p, > + S390TopologySocket *socket) > +{ > + BusChild *kid; > + int l, len = 0; > + > + len += stsi_15_container(p, 1, socket->socket_id); > + p += len; > + > + QTAILQ_FOREACH_REVERSE(kid, &socket->bus->children, sibling) { > + l = stsi_15_cpus(p, S390_TOPOLOGY_CORES(kid->child)); > + p += l; > + len += l; > + } > + return len; > +} > + > +static void insert_stsi_15_1_2(const MachineState *ms, void *p) > +{ > + S390TopologyBook *book; > + SysIB_151x *sysib; > + BusChild *kid; > + int level = 2; > + int len, l; > + > + sysib = (SysIB_151x *)p; > + sysib->mnest = level; > + sysib->mag[TOPOLOGY_NR_MAG2] = ms->smp.sockets; > + sysib->mag[TOPOLOGY_NR_MAG1] = ms->smp.cores; > + > + book = s390_get_topology(); > + len = sizeof(SysIB_151x); > + p += len; > + > + QTAILQ_FOREACH_REVERSE(kid, &book->bus->children, sibling) { > + l = set_socket(ms, p, S390_TOPOLOGY_SOCKET(kid->child)); > + p += l; > + len += l; > + } > + > + sysib->length = len; > +} > + > +static void insert_stsi_15_1_x(S390CPU *cpu, int sel2, __u64 addr, uint8_t ar) > +{ > + const MachineState *machine = MACHINE(qdev_get_machine()); > + void *p; > + int ret, cc; > + > + /* > + * Until the SCLP STSI Facility reporting the MNEST value is used, > + * a sel2 value of 2 is the only value allowed in STSI 15.1.x. > + */ > + if (sel2 != 2) { > + setcc(cpu, 3); > + return; > + } > + > + p = g_malloc0(4096); Use TARGET_PAGE_SIZE instead of magic value 4096? > + insert_stsi_15_1_2(machine, p); Wrong indentation (3 instead of 4 spaces). > + if (s390_is_pv()) { > + ret = s390_cpu_pv_mem_write(cpu, 0, p, 4096); > + } else { > + ret = s390_cpu_virt_mem_write(cpu, addr, ar, p, 4096); TARGET_PAGE_SIZE? > + } > + cc = ret ? 3 : 0; > + setcc(cpu, cc); > + g_free(p); > +} > + > static int handle_stsi(S390CPU *cpu) > { > CPUState *cs = CPU(cpu); > @@ -1920,6 +2017,10 @@ static int handle_stsi(S390CPU *cpu) > /* Only sysib 3.2.2 needs post-handling for now. */ > insert_stsi_3_2_2(cpu, run->s390_stsi.addr, run->s390_stsi.ar); > return 0; > + case 15: > + insert_stsi_15_1_x(cpu, run->s390_stsi.sel2, run->s390_stsi.addr, > + run->s390_stsi.ar); > + return 0; > default: > return 0; > } > Thomas
On 9/7/21 10:00 AM, Thomas Huth wrote: > On 22/07/2021 19.42, Pierre Morel wrote: >> The handling of STSI is enhenced with the interception of the > > s/enhenced/enhanced/ yes, thanks > >> function code 15 for storing CPU topology. ... >> +static void insert_stsi_15_1_x(S390CPU *cpu, int sel2, __u64 addr, >> uint8_t ar) >> +{ >> + const MachineState *machine = MACHINE(qdev_get_machine()); >> + void *p; >> + int ret, cc; >> + >> + /* >> + * Until the SCLP STSI Facility reporting the MNEST value is used, >> + * a sel2 value of 2 is the only value allowed in STSI 15.1.x. >> + */ >> + if (sel2 != 2) { >> + setcc(cpu, 3); >> + return; >> + } >> + >> + p = g_malloc0(4096); > > Use TARGET_PAGE_SIZE instead of magic value 4096? yes > >> + insert_stsi_15_1_2(machine, p); > > Wrong indentation (3 instead of 4 spaces). oh, yes, thanks > >> + if (s390_is_pv()) { >> + ret = s390_cpu_pv_mem_write(cpu, 0, p, 4096); >> + } else { >> + ret = s390_cpu_virt_mem_write(cpu, addr, ar, p, 4096); > > TARGET_PAGE_SIZE? yes, of course. > >> + } >> + cc = ret ? 3 : 0; >> + setcc(cpu, cc); >> + g_free(p); >> +} >> + >> static int handle_stsi(S390CPU *cpu) >> { >> CPUState *cs = CPU(cpu); >> @@ -1920,6 +2017,10 @@ static int handle_stsi(S390CPU *cpu) >> /* Only sysib 3.2.2 needs post-handling for now. */ >> insert_stsi_3_2_2(cpu, run->s390_stsi.addr, run->s390_stsi.ar); >> return 0; >> + case 15: >> + insert_stsi_15_1_x(cpu, run->s390_stsi.sel2, >> run->s390_stsi.addr, >> + run->s390_stsi.ar); >> + return 0; >> default: >> return 0; >> } >> > > Thomas > Thanks for reviewing, Pierre
diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 9a0c13d4ac..0194756e6a 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -52,6 +52,7 @@ #include "hw/s390x/s390-virtio-ccw.h" #include "hw/s390x/s390-virtio-hcall.h" #include "hw/s390x/pv.h" +#include "hw/s390x/cpu-topology.h" #ifndef DEBUG_KVM #define DEBUG_KVM 0 @@ -1907,6 +1908,102 @@ static void insert_stsi_3_2_2(S390CPU *cpu, __u64 addr, uint8_t ar) } } +static int stsi_15_container(void *p, int nl, int id) +{ + SysIBTl_container *tle = (SysIBTl_container *)p; + + tle->nl = nl; + tle->id = id; + + return sizeof(*tle); +} + +static int stsi_15_cpus(void *p, S390TopologyCores *cd) +{ + SysIBTl_cpu *tle = (SysIBTl_cpu *)p; + + tle->nl = 0; + tle->dedicated = cd->dedicated; + tle->polarity = cd->polarity; + tle->type = cd->cputype; + tle->origin = cd->origin; + tle->mask = cd->mask; + + return sizeof(*tle); +} + +static int set_socket(const MachineState *ms, void *p, + S390TopologySocket *socket) +{ + BusChild *kid; + int l, len = 0; + + len += stsi_15_container(p, 1, socket->socket_id); + p += len; + + QTAILQ_FOREACH_REVERSE(kid, &socket->bus->children, sibling) { + l = stsi_15_cpus(p, S390_TOPOLOGY_CORES(kid->child)); + p += l; + len += l; + } + return len; +} + +static void insert_stsi_15_1_2(const MachineState *ms, void *p) +{ + S390TopologyBook *book; + SysIB_151x *sysib; + BusChild *kid; + int level = 2; + int len, l; + + sysib = (SysIB_151x *)p; + sysib->mnest = level; + sysib->mag[TOPOLOGY_NR_MAG2] = ms->smp.sockets; + sysib->mag[TOPOLOGY_NR_MAG1] = ms->smp.cores; + + book = s390_get_topology(); + len = sizeof(SysIB_151x); + p += len; + + QTAILQ_FOREACH_REVERSE(kid, &book->bus->children, sibling) { + l = set_socket(ms, p, S390_TOPOLOGY_SOCKET(kid->child)); + p += l; + len += l; + } + + sysib->length = len; +} + +static void insert_stsi_15_1_x(S390CPU *cpu, int sel2, __u64 addr, uint8_t ar) +{ + const MachineState *machine = MACHINE(qdev_get_machine()); + void *p; + int ret, cc; + + /* + * Until the SCLP STSI Facility reporting the MNEST value is used, + * a sel2 value of 2 is the only value allowed in STSI 15.1.x. + */ + if (sel2 != 2) { + setcc(cpu, 3); + return; + } + + p = g_malloc0(4096); + + insert_stsi_15_1_2(machine, p); + + if (s390_is_pv()) { + ret = s390_cpu_pv_mem_write(cpu, 0, p, 4096); + } else { + ret = s390_cpu_virt_mem_write(cpu, addr, ar, p, 4096); + } + cc = ret ? 3 : 0; + setcc(cpu, cc); + g_free(p); +} + static int handle_stsi(S390CPU *cpu) { CPUState *cs = CPU(cpu); @@ -1920,6 +2017,10 @@ static int handle_stsi(S390CPU *cpu) /* Only sysib 3.2.2 needs post-handling for now. */ insert_stsi_3_2_2(cpu, run->s390_stsi.addr, run->s390_stsi.ar); return 0; + case 15: + insert_stsi_15_1_x(cpu, run->s390_stsi.sel2, run->s390_stsi.addr, + run->s390_stsi.ar); + return 0; default: return 0; }
The handling of STSI is enhenced with the interception of the function code 15 for storing CPU topology. Using the objects built during the pluging of CPU, we build the SYSIB 15_1_x structures. With this patch the maximum MNEST level is 2, this is also the only level allowed and only SYSIB 15_1_2 will be built. Signed-off-by: Pierre Morel <pmorel@linux.ibm.com> --- target/s390x/kvm/kvm.c | 101 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+)