| Message ID | 1612951813-50542-5-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | hw/arm: zynqmp: Implement a CSU DMA model and connect it with GQSPI | expand |
On Wed, Feb 10, 2021 at 06:10:12PM +0800, Bin Meng wrote: > From: Xuzhou Cheng <xuzhou.cheng@windriver.com> > > There are some coding convention warnings in xilinx_spips.c, > as reported by: > > $ ./scripts/checkpatch.pl hw/ssi/xilinx_spips.c > > Let's clean them up. > > Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> > Signed-off-by: Bin Meng <bin.meng@windriver.com> > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > > (no changes since v1) > > hw/ssi/xilinx_spips.c | 23 ++++++++++++++--------- > 1 file changed, 14 insertions(+), 9 deletions(-) > > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c > index a897034..8a0cc22 100644 > --- a/hw/ssi/xilinx_spips.c > +++ b/hw/ssi/xilinx_spips.c > @@ -176,7 +176,8 @@ > FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) > #define R_GQSPI_GFIFO_THRESH (0x150 / 4) > #define R_GQSPI_DATA_STS (0x15c / 4) > -/* We use the snapshot register to hold the core state for the currently > +/* > + * We use the snapshot register to hold the core state for the currently > * or most recently executed command. So the generic fifo format is defined > * for the snapshot register > */ > @@ -424,7 +425,8 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) > xlnx_zynqmp_qspips_update_ixr(s); > } > > -/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) > +/* > + * N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) > * column wise (from element 0 to N-1). num is the length of x, and dir > * reverses the direction of the transform. Best illustrated by example: > * Each digit in the below array is a single bit (num == 3): > @@ -637,8 +639,10 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) > tx_rx[i] = tx; > } > } else { > - /* Extract a dummy byte and generate dummy cycles according to the > - * link state */ > + /* > + * Extract a dummy byte and generate dummy cycles according to the > + * link state > + */ > tx = fifo8_pop(&s->tx_fifo); > dummy_cycles = 8 / s->link_state; > } > @@ -721,8 +725,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) > } > break; > case (SNOOP_ADDR): > - /* Address has been transmitted, transmit dummy cycles now if > - * needed */ > + /* > + * Address has been transmitted, transmit dummy cycles now if needed > + */ > if (s->cmd_dummies < 0) { > s->snoop_state = SNOOP_NONE; > } else { > @@ -876,7 +881,7 @@ static void xlnx_zynqmp_qspips_notify(void *opaque) > } > > static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, > - unsigned size) > + unsigned size) > { > XilinxSPIPS *s = opaque; > uint32_t mask = ~0; > @@ -970,7 +975,7 @@ static uint64_t xlnx_zynqmp_qspips_read(void *opaque, > } > > static void xilinx_spips_write(void *opaque, hwaddr addr, > - uint64_t value, unsigned size) > + uint64_t value, unsigned size) > { > int mask = ~0; > XilinxSPIPS *s = opaque; > @@ -1072,7 +1077,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr addr, > } > > static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, > - uint64_t value, unsigned size) > + uint64_t value, unsigned size) > { > XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); > uint32_t reg = addr / 4; > -- > 2.7.4 >
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index a897034..8a0cc22 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -176,7 +176,8 @@ FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) #define R_GQSPI_GFIFO_THRESH (0x150 / 4) #define R_GQSPI_DATA_STS (0x15c / 4) -/* We use the snapshot register to hold the core state for the currently +/* + * We use the snapshot register to hold the core state for the currently * or most recently executed command. So the generic fifo format is defined * for the snapshot register */ @@ -424,7 +425,8 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) xlnx_zynqmp_qspips_update_ixr(s); } -/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) +/* + * N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) * column wise (from element 0 to N-1). num is the length of x, and dir * reverses the direction of the transform. Best illustrated by example: * Each digit in the below array is a single bit (num == 3): @@ -637,8 +639,10 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) tx_rx[i] = tx; } } else { - /* Extract a dummy byte and generate dummy cycles according to the - * link state */ + /* + * Extract a dummy byte and generate dummy cycles according to the + * link state + */ tx = fifo8_pop(&s->tx_fifo); dummy_cycles = 8 / s->link_state; } @@ -721,8 +725,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } break; case (SNOOP_ADDR): - /* Address has been transmitted, transmit dummy cycles now if - * needed */ + /* + * Address has been transmitted, transmit dummy cycles now if needed + */ if (s->cmd_dummies < 0) { s->snoop_state = SNOOP_NONE; } else { @@ -876,7 +881,7 @@ static void xlnx_zynqmp_qspips_notify(void *opaque) } static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, - unsigned size) + unsigned size) { XilinxSPIPS *s = opaque; uint32_t mask = ~0; @@ -970,7 +975,7 @@ static uint64_t xlnx_zynqmp_qspips_read(void *opaque, } static void xilinx_spips_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) + uint64_t value, unsigned size) { int mask = ~0; XilinxSPIPS *s = opaque; @@ -1072,7 +1077,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr addr, } static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) + uint64_t value, unsigned size) { XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); uint32_t reg = addr / 4;