| Message ID | 1598924352-89526-2-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support | expand |
On 9/1/20 3:38 AM, Bin Meng wrote: > From: Bin Meng <bin.meng@windriver.com> > > Currently the reset vector address is hard-coded in a RISC-V CPU's > instance_init() routine. In a real world we can have 2 exact same > CPUs except for the reset vector address, which is pretty common in > the RISC-V core IP licensing business. > > Normally reset vector address is a configurable parameter. Let's > create a 64-bit property to store the reset vector address which > covers both 32-bit and 64-bit CPUs. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > > (no changes since v1) > > target/riscv/cpu.h | 1 + > target/riscv/cpu.c | 1 + > 2 files changed, 2 insertions(+) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 383808b..dc350f0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -291,6 +291,7 @@ typedef struct RISCVCPU { uint16_t elen; bool mmu; bool pmp; + uint64_t resetvec; } cfg; } RISCVCPU; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 228b9bd..8067a26 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -518,6 +518,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), };