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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id cv7sm2093972pjb.9.2020.07.09.03.05.49 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 09 Jul 2020 03:05:49 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU Date: Thu, 9 Jul 2020 03:05:44 -0700 Message-Id: <1594289144-24723-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1594289144-24723-1-git-send-email-bmeng.cn@gmail.com> References: <1594289144-24723-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng The reset vector codes are subject to change, e.g.: with recent fw_dynamic type image support, it breaks oreboot again. Add a subregion in the MROM, with the size of machine RAM stored, so that we can provide a reliable way for bootloader to detect whether it is running in QEMU. Signed-off-by: Bin Meng --- Changes in v2: - correctly populate the value in little-endian hw/riscv/sifive_u.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 3413369..79519d4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -88,6 +88,7 @@ static const struct MemmapEntry { #define OTP_SERIAL 1 #define GEM_REVISION 0x10070109 +#define MROM_RAMSIZE_OFFSET 0xf8 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) @@ -496,6 +497,26 @@ static void sifive_u_machine_init(MachineState *machine) riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base, memmap[SIFIVE_U_MROM].size, sizeof(reset_vec), kernel_entry); + + /* + * Tell guest the machine ram size at MROM_RAMSIZE_OFFSET. + * On real hardware, the 64-bit value from MROM_RAMSIZE_OFFSET is zero. + * QEMU aware bootloader (e.g.: oreboot, U-Boot) can check value stored + * here to determine whether it is running in QEMU. + */ + + uint32_t ram_size[2] = { + machine->ram_size, + ((uint64_t)(machine->ram_size)) >> 32 + }; + + /* copy in the ram size in little_endian byte order */ + for (i = 0; i < ARRAY_SIZE(ram_size); i++) { + ram_size[i] = cpu_to_le32(ram_size[i]); + } + rom_add_blob_fixed_as("mrom.ram_size", ram_size, sizeof(ram_size), + memmap[SIFIVE_U_MROM].base + MROM_RAMSIZE_OFFSET, + &address_space_memory); } static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)