diff mbox series

[08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs

Message ID 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com
State New
Headers show
Series hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support | expand

Commit Message

Bin Meng June 8, 2020, 2:17 p.m. UTC
From: Bin Meng <bin.meng@windriver.com>

At present the GPIO output IRQs are triggered each time any GPIO
register is written. However this is not correct. We should only
trigger the output IRQ when the pin is configured as output enable.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 hw/riscv/sifive_gpio.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Alistair Francis June 15, 2020, 4:28 p.m. UTC | #1
On Mon, Jun 8, 2020 at 7:24 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> At present the GPIO output IRQs are triggered each time any GPIO
> register is written. However this is not correct. We should only
> trigger the output IRQ when the pin is configured as output enable.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/riscv/sifive_gpio.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
> index 0d0fd2b..aac6b44 100644
> --- a/hw/riscv/sifive_gpio.c
> +++ b/hw/riscv/sifive_gpio.c
> @@ -76,7 +76,9 @@ static void update_state(SIFIVEGPIOState *s)
>              actual_value = pull;
>          }
>
> -        qemu_set_irq(s->output[i], actual_value);
> +        if (output_en) {
> +            qemu_set_irq(s->output[i], actual_value);
> +        }
>
>          /* Input value */
>          ival = input_en && actual_value;
> --
> 2.7.4
>
>
diff mbox series

Patch

diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
index 0d0fd2b..aac6b44 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/riscv/sifive_gpio.c
@@ -76,7 +76,9 @@  static void update_state(SIFIVEGPIOState *s)
             actual_value = pull;
         }
 
-        qemu_set_irq(s->output[i], actual_value);
+        if (output_en) {
+            qemu_set_irq(s->output[i], actual_value);
+        }
 
         /* Input value */
         ival = input_en && actual_value;