Message ID | 1591342707-9729-3-git-send-email-bmeng.cn@gmail.com |
---|---|
State | Superseded |
Headers | show |
Series | [1/4] riscv: Generalize CPU init routine for the base CPU | expand |
On Fri, Jun 5, 2020 at 12:40 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > There is no need to have two functions that have almost the same > codes for 32-bit and 64-bit imacu CPUs. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > --- > > target/riscv/cpu.c | 31 ++++++++++--------------------- > 1 file changed, 10 insertions(+), 21 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e66488f..c5c2abc 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -142,23 +142,23 @@ static void rvnn_gcsu_priv1_10_0_cpu_init(Object *obj) > set_resetvec(env, DEFAULT_RSTVEC); > } > > -#if defined(TARGET_RISCV32) > - > -static void rv32imcu_nommu_cpu_init(Object *obj) > +static void rvnn_imacu_nommu_cpu_init(Object *obj) Same request with rvxx_* Otherwise: Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > - set_misa(env, RV32 | RVI | RVM | RVC | RVU); > + set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > - set_resetvec(env, 0x8090); > + set_resetvec(env, DEFAULT_RSTVEC); > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > } > > -static void rv32imacu_nommu_cpu_init(Object *obj) > +#if defined(TARGET_RISCV32) > + > +static void rv32imcu_nommu_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > - set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); > + set_misa(env, RV32 | RVI | RVM | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > - set_resetvec(env, DEFAULT_RSTVEC); > + set_resetvec(env, 0x8090); > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > } > > @@ -171,17 +171,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj) > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > } > > -#elif defined(TARGET_RISCV64) > - > -static void rv64imacu_nommu_cpu_init(Object *obj) > -{ > - CPURISCVState *env = &RISCV_CPU(obj)->env; > - set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); > - set_priv_version(env, PRIV_VERSION_1_10_0); > - set_resetvec(env, DEFAULT_RSTVEC); > - qdev_prop_set_bit(DEVICE(obj), "mmu", false); > -} > - > #endif > > static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) > @@ -587,12 +576,12 @@ static const TypeInfo riscv_cpu_type_infos[] = { > #if defined(TARGET_RISCV32) > DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvnn_imacu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvnn_gcsu_priv1_10_0_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvnn_imacu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvnn_gcsu_priv1_10_0_cpu_init), > #endif > }; > -- > 2.7.4 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e66488f..c5c2abc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -142,23 +142,23 @@ static void rvnn_gcsu_priv1_10_0_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } -#if defined(TARGET_RISCV32) - -static void rv32imcu_nommu_cpu_init(Object *obj) +static void rvnn_imacu_nommu_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVC | RVU); + set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, 0x8090); + set_resetvec(env, DEFAULT_RSTVEC); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } -static void rv32imacu_nommu_cpu_init(Object *obj) +#if defined(TARGET_RISCV32) + +static void rv32imcu_nommu_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); + set_misa(env, RV32 | RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, DEFAULT_RSTVEC); + set_resetvec(env, 0x8090); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -171,17 +171,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj) qdev_prop_set_bit(DEVICE(obj), "mmu", false); } -#elif defined(TARGET_RISCV64) - -static void rv64imacu_nommu_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, DEFAULT_RSTVEC); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); -} - #endif static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -587,12 +576,12 @@ static const TypeInfo riscv_cpu_type_infos[] = { #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvnn_imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvnn_gcsu_priv1_10_0_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvnn_imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvnn_gcsu_priv1_10_0_cpu_init), #endif };