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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id z24sm6004349pfk.46.2020.03.07.04.48.43 (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 07 Mar 2020 04:48:44 -0800 (PST) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH] hw/riscv: Generate correct "mmu-type" for 32-bit machines Date: Sat, 7 Mar 2020 04:48:39 -0800 Message-Id: <1583585319-26603-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" 32-bit machine should have its CPU's "mmu-type" set to "riscv,sv32". Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 4 ++++ hw/riscv/spike.c | 4 ++++ hw/riscv/virt.c | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d318988..26ea777 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -159,7 +159,11 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_add_subnode(fdt, nodename); /* cpu 0 is the management hart that does not have mmu */ if (cpu != 0) { +#if defined(TARGET_RISCV32) + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); +#else qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); +#endif isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); } else { isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 8823681..6f9a1ba 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -102,7 +102,11 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); char *isa = riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); +#if defined(TARGET_RISCV32) + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); +#else qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); +#endif qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 7f9e1e5..57f532a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -229,7 +229,11 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); char *isa = riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); +#if defined(TARGET_RISCV32) + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); +#else qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); +#endif qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); qemu_fdt_setprop_string(fdt, nodename, "status", "okay");