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Fri, 6 Sep 2019 19:12:33 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::6c7c:4b6d:f136:1bf8]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::6c7c:4b6d:f136:1bf8%3]) with mapi id 15.20.2220.022; Fri, 6 Sep 2019 19:12:33 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 08/16] i386: Cleanup and use the new epyc mode topology functions Thread-Index: AQHVZOcJUr5O2hUIukO4Iv4t3TEIVA== Date: Fri, 6 Sep 2019 19:12:33 +0000 Message-ID: <156779715031.21957.17374671669134234845.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0043.namprd02.prod.outlook.com (2603:10b6:803:2e::29) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1179; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 84NGGFez93ks1F+zr+lG9uzFgsQQiljPAD0E7DCfVjqrLYaBi4cqsZuS6YE3VABKXw1K1kfGc/xkOQIcSkkun7RhhaSvZyFX39uxdGboQJY0wHzhtam4URSKpgLVfxyHbx3Jozkv/X8DTdwQ0+Ovvg8RhRiY/iQ5fM3EQ7tDDFhLJKquRKO5fQSIwPe+P39vP3FAv9DWn5Sw7VDIRDZPtq0i/Z2cqLVJ2CZlr88viYmBtSec4WQaQEHxg4JPmjtt82Uiq8+zlhx3ccOUQUX5sDz0IkCfR0O7Yxfb6VpuFNaXOyFAh5Tj8tWt5ZEBuRhC2LDPk9oATzLHNmKw2BcjeJU0XesKKH8JNxb9R3Mt3VDBnNivOWt8+feIuIo9JHmwbvq6wfz/4tQS/t0p9MQxLtR40jEwRUqIBuJG4WaWwpM= Content-ID: <2E1F7309F869144FA47702FF2F1055EF@namprd12.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 82f0a3e5-b343-4ba6-0a78-08d732fe2ad9 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:12:33.2805 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: u/VkRXBi/+kEcqF95VL3d+YixiYBeZq16C3MG4c3+5u5i/sKGx3A1GXuWUYE/UJ8 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1179 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.82.75 Subject: [Qemu-devel] [RFC 2 PATCH 08/16] i386: Cleanup and use the new epyc mode topology functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use the new epyc mode functions and delete the unused code. Signed-off-by: Babu Moger --- target/i386/cpu.c | 171 +++++++++++++++-------------------------------------- 1 file changed, 48 insertions(+), 123 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ca02bc21ec..f25491a029 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -28,6 +28,7 @@ #include "sysemu/kvm.h" #include "sysemu/hvf.h" #include "sysemu/cpus.h" +#include "sysemu/numa.h" #include "kvm_i386.h" #include "sev_i386.h" @@ -338,67 +339,19 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l2, } } -/* - * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E - * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3. - * Define the constants to build the cpu topology. Right now, TOPOEXT - * feature is enabled only on EPYC. So, these constants are based on - * EPYC supported configurations. We may need to handle the cases if - * these values change in future. - */ -/* Maximum core complexes in a node */ -#define MAX_CCX 2 -/* Maximum cores in a core complex */ -#define MAX_CORES_IN_CCX 4 -/* Maximum cores in a node */ -#define MAX_CORES_IN_NODE 8 -/* Maximum nodes in a socket */ -#define MAX_NODES_PER_SOCKET 4 - -/* - * Figure out the number of nodes required to build this config. - * Max cores in a node is 8 - */ -static int nodes_in_socket(int nr_cores) -{ - int nodes; - - nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE); - - /* Hardware does not support config with 3 nodes, return 4 in that case */ - return (nodes == 3) ? 4 : nodes; -} - -/* - * Decide the number of cores in a core complex with the given nr_cores using - * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and - * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible - * L3 cache is shared across all cores in a core complex. So, this will also - * tell us how many cores are sharing the L3 cache. - */ -static int cores_in_core_complex(int nr_cores) -{ - int nodes; - - /* Check if we can fit all the cores in one core complex */ - if (nr_cores <= MAX_CORES_IN_CCX) { - return nr_cores; - } - /* Get the number of nodes required to build this config */ - nodes = nodes_in_socket(nr_cores); - - /* - * Divide the cores accros all the core complexes - * Return rounded up value - */ - return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX); -} - /* Encode cache info for CPUID[8000001D] */ -static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, - uint32_t *eax, uint32_t *ebx, - uint32_t *ecx, uint32_t *edx) +static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) { + MachineState *ms = MACHINE(qdev_get_machine()); + X86CPUTopoInfo topo_info = { + .numa_nodes = nb_numa_nodes, + .nr_sockets = ms->smp.sockets, + .nr_cores = ms->smp.cores, + .nr_threads = ms->smp.threads, + }; + uint32_t l3_cores; assert(cache->size == cache->line_size * cache->associativity * cache->partitions * cache->sets); @@ -408,10 +361,10 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, /* L3 is shared among multiple cores */ if (cache->level == 3) { - l3_cores = cores_in_core_complex(cs->nr_cores); - *eax |= ((l3_cores * cs->nr_threads) - 1) << 14; + l3_cores = cores_in_ccx(&topo_info); + *eax |= ((l3_cores * topo_info.nr_threads) - 1) << 14; } else { - *eax |= ((cs->nr_threads - 1) << 14); + *eax |= ((topo_info.nr_threads - 1) << 14); } assert(cache->line_size > 0); @@ -431,56 +384,28 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); } -/* Data structure to hold the configuration info for a given core index */ -struct core_topology { - /* core complex id of the current core index */ - int ccx_id; - /* - * Adjusted core index for this core in the topology - * This can be 0,1,2,3 with max 4 cores in a core complex - */ - int core_id; - /* Node id for this core index */ - int node_id; - /* Number of nodes in this config */ - int num_nodes; -}; - -/* - * Build the configuration closely match the EPYC hardware. Using the EPYC - * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE) - * right now. This could change in future. - * nr_cores : Total number of cores in the config - * core_id : Core index of the current CPU - * topo : Data structure to hold all the config info for this core index - */ -static void build_core_topology(int nr_cores, int core_id, - struct core_topology *topo) -{ - int nodes, cores_in_ccx; - - /* First get the number of nodes required */ - nodes = nodes_in_socket(nr_cores); - - cores_in_ccx = cores_in_core_complex(nr_cores); - - topo->node_id = core_id / (cores_in_ccx * MAX_CCX); - topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx; - topo->core_id = core_id % cores_in_ccx; - topo->num_nodes = nodes; -} - /* Encode cache info for CPUID[8000001E] */ -static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, - uint32_t *eax, uint32_t *ebx, - uint32_t *ecx, uint32_t *edx) +static void encode_topo_cpuid8000001e(CPUX86State *env, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) { - struct core_topology topo = {0}; - unsigned long nodes; - int shift; + X86CPUTopoIDs topo_ids = { 0 }; + unsigned long nodes, shift; + X86CPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); + MachineState *ms = MACHINE(qdev_get_machine()); + X86CPUTopoInfo topo_info = { + .numa_nodes = nb_numa_nodes, + .nr_sockets = ms->smp.sockets, + .nr_cores = ms->smp.cores, + .nr_threads = ms->smp.threads, + }; + + nodes = nodes_in_pkg(&topo_info); + x86_topo_ids_from_idx_epyc(&topo_info, cs->cpu_index, &topo_ids); - build_core_topology(cs->nr_cores, cpu->core_id, &topo); *eax = cpu->apic_id; + /* * CPUID_Fn8000001E_EBX * 31:16 Reserved @@ -496,11 +421,12 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, * 3 Core complex id * 1:0 Core id */ - if (cs->nr_threads - 1) { - *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) | - (topo.ccx_id << 2) | topo.core_id; + if (topo_info.nr_threads - 1) { + *ebx = ((topo_info.nr_threads - 1) << 8) | (topo_ids.node_id << 3) | + (topo_ids.ccx_id << 2) | topo_ids.core_id; } else { - *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id; + *ebx = (topo_ids.node_id << 4) | (topo_ids.ccx_id << 3) | + topo_ids.core_id; } /* * CPUID_Fn8000001E_ECX @@ -510,9 +436,8 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, * 2 Socket id * 1:0 Node id */ - if (topo.num_nodes <= 4) { - *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) | - topo.node_id; + if (nodes <= 4) { + *ecx = ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.node_id; } else { /* * Node id fix up. Actual hardware supports up to 4 nodes. But with @@ -527,12 +452,12 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, * number of nodes. find_last_bit returns last set bit(0 based). Left * shift(+1) the socket id to represent all the nodes. */ - nodes = topo.num_nodes - 1; + nodes = nodes - 1; shift = find_last_bit(&nodes, 8); - *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) | - topo.node_id; + *ecx = (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) | topo_ids.node_id; } *edx = 0; + } /* @@ -4580,19 +4505,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs, + encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs, + encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs, + encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs, + encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, eax, ebx, ecx, edx); break; default: /* end of info */ @@ -4602,7 +4527,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 0x8000001E: assert(cpu->core_id <= 255); - encode_topo_cpuid8000001e(cs, cpu, + encode_topo_cpuid8000001e(env, eax, ebx, ecx, edx); break; case 0xC0000000: