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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id 23sm80222524pfn.176.2019.08.02.17.27.37 (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 02 Aug 2019 17:27:37 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 2 Aug 2019 17:27:32 -0700 Message-Id: <1564792052-6469-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Some of the SoC IP block sizes are wrong. Correct them according to the FE310 manual. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 2a499d8..9655847 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -53,13 +53,13 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } sifive_e_memmap[] = { - [SIFIVE_E_DEBUG] = { 0x0, 0x100 }, + [SIFIVE_E_DEBUG] = { 0x0, 0x1000 }, [SIFIVE_E_MROM] = { 0x1000, 0x2000 }, [SIFIVE_E_OTP] = { 0x20000, 0x2000 }, [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 }, - [SIFIVE_E_AON] = { 0x10000000, 0x8000 }, - [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 }, + [SIFIVE_E_AON] = { 0x10000000, 0x1000 }, + [SIFIVE_E_PRCI] = { 0x10008000, 0x1000 }, [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 }, [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 }, [SIFIVE_E_UART0] = { 0x10013000, 0x1000 },