From patchwork Thu Oct 5 16:24:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Igor Mammedov X-Patchwork-Id: 821939 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y7JPH35lNz9t16 for ; Fri, 6 Oct 2017 03:38:43 +1100 (AEDT) Received: from localhost ([::1]:40831 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e09AX-0005Wo-Cl for incoming@patchwork.ozlabs.org; Thu, 05 Oct 2017 12:38:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e08xo-0003NJ-5Y for qemu-devel@nongnu.org; Thu, 05 Oct 2017 12:25:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e08xm-0003pZ-Q5 for qemu-devel@nongnu.org; Thu, 05 Oct 2017 12:25:32 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36926) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e08xm-0003nq-Gj; Thu, 05 Oct 2017 12:25:30 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7EF808210D; Thu, 5 Oct 2017 16:25:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 7EF808210D Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=imammedo@redhat.com Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.34.112.60]) by smtp.corp.redhat.com (Postfix) with ESMTP id 33F8B5C54B; Thu, 5 Oct 2017 16:25:28 +0000 (UTC) From: Igor Mammedov To: qemu-devel@nongnu.org Date: Thu, 5 Oct 2017 18:24:49 +0200 Message-Id: <1507220690-265042-23-git-send-email-imammedo@redhat.com> In-Reply-To: <1507220690-265042-1-git-send-email-imammedo@redhat.com> References: <1507220690-265042-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Thu, 05 Oct 2017 16:25:29 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 22/23] ppc: pnv: drop PnvChipClass::cpu_model field X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:ppce500" , "Edgar E. Iglesias" , =?utf-8?q?Herv=C3=A9_Poussineau?= , Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" deduce core type directly from chip type instead of maintaining type mapping in PnvChipClass::cpu_model. Signed-off-by: Igor Mammedov Reviewed-by: Cédric Le Goater --- include/hw/ppc/pnv.h | 1 - include/hw/ppc/pnv_core.h | 1 - hw/ppc/pnv.c | 25 +++++++++++++------------ hw/ppc/pnv_core.c | 5 ----- 4 files changed, 13 insertions(+), 19 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index d82eee1..20244da 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -69,7 +69,6 @@ typedef struct PnvChipClass { SysBusDeviceClass parent_class; /*< public >*/ - const char *cpu_model; PnvChipType chip_type; uint64_t chip_cfam_id; uint64_t cores_mask; diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index a336a1f..e337af7 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -46,6 +46,5 @@ typedef struct PnvCoreClass { #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE #define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX -extern char *pnv_core_typename(const char *model); #endif /* _PPC_PNV_CORE_H */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 9c5eb7c..ab7083b 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -55,6 +55,16 @@ #define KERNEL_LOAD_ADDR 0x20000000 #define INITRD_LOAD_ADDR 0x40000000 +static const char *pvn_chip_core_typename(const PnvChip *o) +{ + const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); + int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); + char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); + const char *core_type = object_class_get_name(object_class_by_name(s)); + g_free(s); + return core_type; +} + /* * On Power Systems E880 (POWER8), the max cpus (threads) should be : * 4 * 4 sockets * 12 cores * 8 threads = 1536 @@ -270,8 +280,7 @@ static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) static void powernv_populate_chip(PnvChip *chip, void *fdt) { - PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); - char *typename = pnv_core_typename(pcc->cpu_model); + const char *typename = pvn_chip_core_typename(chip); size_t typesize = object_type_get_instance_size(typename); int i; @@ -301,7 +310,6 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt) powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start, chip->ram_size); } - g_free(typename); } static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off) @@ -713,7 +721,6 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvChipClass *k = PNV_CHIP_CLASS(klass); - k->cpu_model = "power8e_v2.1"; k->chip_type = PNV_CHIP_POWER8E; k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask = POWER8E_CORE_MASK; @@ -735,7 +742,6 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvChipClass *k = PNV_CHIP_CLASS(klass); - k->cpu_model = "power8_v2.0"; k->chip_type = PNV_CHIP_POWER8; k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask = POWER8_CORE_MASK; @@ -757,7 +763,6 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvChipClass *k = PNV_CHIP_CLASS(klass); - k->cpu_model = "power8nvl_v1.0"; k->chip_type = PNV_CHIP_POWER8NVL; k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask = POWER8_CORE_MASK; @@ -779,7 +784,6 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvChipClass *k = PNV_CHIP_CLASS(klass); - k->cpu_model = "power9_v1.0"; k->chip_type = PNV_CHIP_POWER9; k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ k->cores_mask = POWER9_CORE_MASK; @@ -854,7 +858,7 @@ static void pnv_chip_init(Object *obj) static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) { PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); - char *typename = pnv_core_typename(pcc->cpu_model); + const char *typename = pvn_chip_core_typename(chip); size_t typesize = object_type_get_instance_size(typename); int i, j; char *name; @@ -879,8 +883,6 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->mmio); } } - - g_free(typename); } static void pnv_chip_realize(DeviceState *dev, Error **errp) @@ -888,7 +890,7 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp) PnvChip *chip = PNV_CHIP(dev); Error *error = NULL; PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); - char *typename = pnv_core_typename(pcc->cpu_model); + const char *typename = pvn_chip_core_typename(chip); size_t typesize = object_type_get_instance_size(typename); int i, core_hwid; @@ -947,7 +949,6 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp) &PNV_CORE(pnv_core)->xscom_regs); i++; } - g_free(typename); /* Create LPC controller */ object_property_set_bool(OBJECT(&chip->lpc), true, "realized", diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 000c87e..621b69e 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -246,9 +246,4 @@ static const TypeInfo pnv_core_infos[] = { DEFINE_PNV_CORE_TYPE("power9_v1.0"), }; -char *pnv_core_typename(const char *model) -{ - return g_strdup_printf(PNV_CORE_TYPE_NAME("%s"), model); -} - DEFINE_TYPES(pnv_core_infos)