From patchwork Thu Oct 5 13:50:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Igor Mammedov X-Patchwork-Id: 821828 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y7FF60BTMz9t2Z for ; Fri, 6 Oct 2017 01:16:26 +1100 (AEDT) Received: from localhost ([::1]:40044 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e06wq-0003HT-39 for incoming@patchwork.ozlabs.org; Thu, 05 Oct 2017 10:16:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52614) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e06Yy-0007Ur-94 for qemu-devel@nongnu.org; Thu, 05 Oct 2017 09:51:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e06Yx-000056-7p for qemu-devel@nongnu.org; Thu, 05 Oct 2017 09:51:44 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52698) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e06Yw-0008W6-VL for qemu-devel@nongnu.org; Thu, 05 Oct 2017 09:51:43 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id AAC347F41E; Thu, 5 Oct 2017 13:51:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com AAC347F41E Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=imammedo@redhat.com Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.34.112.60]) by smtp.corp.redhat.com (Postfix) with ESMTP id C2CE65C88F; Thu, 5 Oct 2017 13:51:40 +0000 (UTC) From: Igor Mammedov To: qemu-devel@nongnu.org Date: Thu, 5 Oct 2017 15:50:55 +0200 Message-Id: <1507211474-188400-22-git-send-email-imammedo@redhat.com> In-Reply-To: <1507211474-188400-1-git-send-email-imammedo@redhat.com> References: <1507211474-188400-1-git-send-email-imammedo@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Thu, 05 Oct 2017 13:51:42 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 21/40] sh4: cleanup cpu type name composition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" introduce SUPERH_CPU_TYPE_NAME macro and use it to construct cpu type names. While at it move cpu type_infos into one array and register it directly with type_init_from_array() instead of custom superh_cpu_register_types() Signed-off-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daudé --- v2: rename type_init_from_array into DEFINE_TYPES CC: aurelien@aurel32.net --- target/sh4/cpu-qom.h | 6 ++--- target/sh4/cpu.h | 3 +++ target/sh4/cpu.c | 63 +++++++++++++++++++++------------------------------- 3 files changed, 31 insertions(+), 41 deletions(-) diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h index 01abb20..17deeb6 100644 --- a/target/sh4/cpu-qom.h +++ b/target/sh4/cpu-qom.h @@ -24,9 +24,9 @@ #define TYPE_SUPERH_CPU "superh-cpu" -#define TYPE_SH7750R_CPU "sh7750r-" TYPE_SUPERH_CPU -#define TYPE_SH7751R_CPU "sh7751r-" TYPE_SUPERH_CPU -#define TYPE_SH7785_CPU "sh7785-" TYPE_SUPERH_CPU +#define TYPE_SH7750R_CPU SUPERH_CPU_TYPE_NAME("sh7750r") +#define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r") +#define TYPE_SH7785_CPU SUPERH_CPU_TYPE_NAME("sh7785") #define SUPERH_CPU_CLASS(klass) \ OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 79f85d3..a25a3f6 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -270,6 +270,9 @@ void cpu_load_tlb(CPUSH4State * env); #define cpu_init(cpu_model) cpu_generic_init(TYPE_SUPERH_CPU, cpu_model) +#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU +#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX + #define cpu_signal_handler cpu_sh4_signal_handler #define cpu_list sh4_cpu_list diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 252440e..72f1dec 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -172,13 +172,6 @@ static void sh7750r_class_init(ObjectClass *oc, void *data) scc->cvr = 0x00110000; } -static const TypeInfo sh7750r_type_info = { - .name = TYPE_SH7750R_CPU, - .parent = TYPE_SUPERH_CPU, - .class_init = sh7750r_class_init, - .instance_init = sh7750r_cpu_initfn, -}; - static void sh7751r_cpu_initfn(Object *obj) { SuperHCPU *cpu = SUPERH_CPU(obj); @@ -198,13 +191,6 @@ static void sh7751r_class_init(ObjectClass *oc, void *data) scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ } -static const TypeInfo sh7751r_type_info = { - .name = TYPE_SH7751R_CPU, - .parent = TYPE_SUPERH_CPU, - .class_init = sh7751r_class_init, - .instance_init = sh7751r_cpu_initfn, -}; - static void sh7785_cpu_initfn(Object *obj) { SuperHCPU *cpu = SUPERH_CPU(obj); @@ -224,13 +210,6 @@ static void sh7785_class_init(ObjectClass *oc, void *data) scc->cvr = 0x71440211; } -static const TypeInfo sh7785_type_info = { - .name = TYPE_SH7785_CPU, - .parent = TYPE_SUPERH_CPU, - .class_init = sh7785_class_init, - .instance_init = sh7785_cpu_initfn, -}; - static void superh_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -303,22 +282,30 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) dc->vmsd = &vmstate_sh_cpu; } -static const TypeInfo superh_cpu_type_info = { - .name = TYPE_SUPERH_CPU, - .parent = TYPE_CPU, - .instance_size = sizeof(SuperHCPU), - .instance_init = superh_cpu_initfn, - .abstract = true, - .class_size = sizeof(SuperHCPUClass), - .class_init = superh_cpu_class_init, -}; +#define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ + { \ + .name = type_name, \ + .parent = TYPE_SUPERH_CPU, \ + .class_init = cinit, \ + .instance_init = initfn, \ + } +static const TypeInfo superh_cpu_type_infos[] = { + { + .name = TYPE_SUPERH_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(SuperHCPU), + .instance_init = superh_cpu_initfn, + .abstract = true, + .class_size = sizeof(SuperHCPUClass), + .class_init = superh_cpu_class_init, + }, + DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init, + sh7750r_cpu_initfn), + DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init, + sh7751r_cpu_initfn), + DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init, + sh7785_cpu_initfn), -static void superh_cpu_register_types(void) -{ - type_register_static(&superh_cpu_type_info); - type_register_static(&sh7750r_type_info); - type_register_static(&sh7751r_type_info); - type_register_static(&sh7785_type_info); -} +}; -type_init(superh_cpu_register_types) +DEFINE_TYPES(superh_cpu_type_infos)