From patchwork Thu Oct 5 13:50:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Igor Mammedov X-Patchwork-Id: 821819 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y7F710yjbz9t2Z for ; Fri, 6 Oct 2017 01:11:09 +1100 (AEDT) Received: from localhost ([::1]:40020 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e06rj-0006lv-55 for incoming@patchwork.ozlabs.org; Thu, 05 Oct 2017 10:11:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52574) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e06Yu-0007Qh-L1 for qemu-devel@nongnu.org; Thu, 05 Oct 2017 09:51:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e06Ys-0008Rj-C8 for qemu-devel@nongnu.org; Thu, 05 Oct 2017 09:51:40 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34954) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e06Ys-0008Qp-3m for qemu-devel@nongnu.org; Thu, 05 Oct 2017 09:51:38 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id AB537C04AC4E; Thu, 5 Oct 2017 13:51:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com AB537C04AC4E Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=imammedo@redhat.com Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.34.112.60]) by smtp.corp.redhat.com (Postfix) with ESMTP id C64365C88F; Thu, 5 Oct 2017 13:51:35 +0000 (UTC) From: Igor Mammedov To: qemu-devel@nongnu.org Date: Thu, 5 Oct 2017 15:50:51 +0200 Message-Id: <1507211474-188400-18-git-send-email-imammedo@redhat.com> In-Reply-To: <1507211474-188400-1-git-send-email-imammedo@redhat.com> References: <1507211474-188400-1-git-send-email-imammedo@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Thu, 05 Oct 2017 13:51:37 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 17/40] openrisc: cleanup cpu type name composition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" use new OPENRISC_CPU_TYPE_NAME to compose CPU type name and get rid of intermediate OpenRISCCPUInfo/openrisc_cpu_register_types() which is replaced by static TypeInfo array. Signed-off-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daudé Acked-by: Stafford Horne --- v2: rename type_init_from_array into DEFINE_TYPES CC: shorne@gmail.com --- target/openrisc/cpu.h | 3 +++ target/openrisc/cpu.c | 69 +++++++++++++++++---------------------------------- 2 files changed, 26 insertions(+), 46 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index f51b89a..576cf66 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -390,6 +390,9 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, #define cpu_init(cpu_model) cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model) +#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU +#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX + #include "exec/cpu-all.h" #define TB_FLAGS_DFLAG 1 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index af9cdcc..629831a 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -108,7 +108,7 @@ static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) ObjectClass *oc; char *typename; - typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model); + typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || @@ -133,16 +133,6 @@ static void openrisc_any_initfn(Object *obj) cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP; } -typedef struct OpenRISCCPUInfo { - const char *name; - void (*initfn)(Object *obj); -} OpenRISCCPUInfo; - -static const OpenRISCCPUInfo openrisc_cpus[] = { - { .name = "or1200", .initfn = or1200_initfn }, - { .name = "any", .initfn = openrisc_any_initfn }, -}; - static void openrisc_cpu_class_init(ObjectClass *oc, void *data) { OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); @@ -172,40 +162,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_num_core_regs = 32 + 3; } -static void cpu_register(const OpenRISCCPUInfo *info) -{ - TypeInfo type_info = { - .parent = TYPE_OPENRISC_CPU, - .instance_size = sizeof(OpenRISCCPU), - .instance_init = info->initfn, - .class_size = sizeof(OpenRISCCPUClass), - }; - - type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name); - type_register(&type_info); - g_free((void *)type_info.name); -} - -static const TypeInfo openrisc_cpu_type_info = { - .name = TYPE_OPENRISC_CPU, - .parent = TYPE_CPU, - .instance_size = sizeof(OpenRISCCPU), - .instance_init = openrisc_cpu_initfn, - .abstract = true, - .class_size = sizeof(OpenRISCCPUClass), - .class_init = openrisc_cpu_class_init, -}; - -static void openrisc_cpu_register_types(void) -{ - int i; - - type_register_static(&openrisc_cpu_type_info); - for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) { - cpu_register(&openrisc_cpus[i]); - } -} - /* Sort alphabetically by type name, except for "any". */ static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) { @@ -254,4 +210,25 @@ void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf) g_slist_free(list); } -type_init(openrisc_cpu_register_types) +#define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ + { \ + .parent = TYPE_OPENRISC_CPU, \ + .instance_init = initfn, \ + .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ + } + +static const TypeInfo openrisc_cpus_type_infos[] = { + { /* base class should be registered first */ + .name = TYPE_OPENRISC_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(OpenRISCCPU), + .instance_init = openrisc_cpu_initfn, + .abstract = true, + .class_size = sizeof(OpenRISCCPUClass), + .class_init = openrisc_cpu_class_init, + }, + DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), + DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), +}; + +DEFINE_TYPES(openrisc_cpus_type_infos)