[4/9] target-ppc: Add xscmpoqp and xscmpuqp instructions

From: Bharata B Rao <bharata@linux.vnet.ibm.com>

xscmpoqp - VSX Scalar Compare Ordered Quad-Precision
xscmpuqp - VSX Scalar Compare Unordered Quad-Precision

Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/fpu_helper.c             | 52 +++++++++++++++++++++++++++++++++++++
 target-ppc/helper.h                 |  2 ++
 target-ppc/translate/vsx-impl.inc.c |  2 ++
 target-ppc/translate/vsx-ops.inc.c  |  2 ++
 4 files changed, 58 insertions(+)

On Tue, Nov 22, 2016 at 05:16:00PM +0530, Nikunj A Dadhania wrote:
> From: Bharata B Rao <bharata@linux.vnet.ibm.com>
> 
> xscmpoqp - VSX Scalar Compare Ordered Quad-Precision
> xscmpuqp - VSX Scalar Compare Unordered Quad-Precision
> 
> Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
>  target-ppc/fpu_helper.c             | 52 +++++++++++++++++++++++++++++++++++++
>  target-ppc/helper.h                 |  2 ++
>  target-ppc/translate/vsx-impl.inc.c |  2 ++
>  target-ppc/translate/vsx-ops.inc.c  |  2 ++
>  4 files changed, 58 insertions(+)
> 
> diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
> index b1c5a07..28c1fea 100644
> --- a/target-ppc/fpu_helper.c
> +++ b/target-ppc/fpu_helper.c
> @@ -2518,6 +2518,58 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)                      \
>  VSX_SCALAR_CMP(xscmpodp, 1)
>  VSX_SCALAR_CMP(xscmpudp, 0)
>  
> +#define VSX_SCALAR_CMPQ(op, ordered)                                    \
> +void helper_##op(CPUPPCState *env, uint32_t opcode)                     \
> +{                                                                       \
> +    ppc_vsr_t xa, xb;                                                   \
> +    uint32_t cc = 0;                                                    \
> +    bool vxsnan_flag = false, vxvc_flag = false;                        \
> +    float128 a, b;                                                      \
> +                                                                        \
> +    helper_reset_fpstatus(env);                                         \
> +    getVSR(rA(opcode) + 32, &xa, env);                                  \
> +    getVSR(rB(opcode) + 32, &xb, env);                                  \
> +                                                                        \
> +    a = make_float128(xa.VsrD(0), xa.VsrD(1));                          \
> +    b = make_float128(xb.VsrD(0), xb.VsrD(1));                          \
> +                                                                        \
> +    if (float128_is_signaling_nan(a, &env->fp_status) ||                \
> +        float128_is_signaling_nan(b, &env->fp_status)) {                \
> +        vxsnan_flag = true;                                             \
> +        cc = 1;                                                         \
> +        if (fpscr_ve == 0 && ordered) {                                 \
> +            vxvc_flag = true;                                           \
> +        }                                                               \
> +    } else if (ordered && (float128_is_quiet_nan(a, &env->fp_status)    \
> +                           || float128_is_quiet_nan(b, &env->fp_status))) { \
> +        cc = 1;                                                         \

Please use symbolic constants for the CC bits.

> +        vxvc_flag = true;                                               \
> +    }                                                                   \
> +    if (vxsnan_flag) {                                                  \
> +        float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);          \
> +    }                                                                   \
> +    if (vxvc_flag) {                                                    \
> +        float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0);            \
> +    }                                                                   \
> +                                                                        \
> +    if (float128_lt(a, b, &env->fp_status)) {                           \
> +        cc |= 8;                                                        \
> +    } else if (!float128_le(a, b, &env->fp_status)) {                   \
> +        cc |= 4;                                                        \
> +    } else {                                                            \
> +        cc |= 2;                                                        \
> +    }                                                                   \
> +                                                                        \
> +    env->fpscr &= ~(0x0F << FPSCR_FPRF);                                \
> +    env->fpscr |= cc << FPSCR_FPRF;                                     \
> +    env->crf[BF(opcode)] = cc;                                          \
> +                                                                        \
> +    float_check_status(env);                                            \
> +}
> +
> +VSX_SCALAR_CMPQ(xscmpoqp, 1)
> +VSX_SCALAR_CMPQ(xscmpuqp, 0)
> +
>  /* VSX_MAX_MIN - VSX floating point maximum/minimum
>   *   name  - instruction mnemonic
>   *   op    - operation (max or min)
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index ba42015..3b26678 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -408,6 +408,8 @@ DEF_HELPER_2(xscmpexpdp, void, env, i32)
>  DEF_HELPER_2(xscmpexpqp, void, env, i32)
>  DEF_HELPER_2(xscmpodp, void, env, i32)
>  DEF_HELPER_2(xscmpudp, void, env, i32)
> +DEF_HELPER_2(xscmpoqp, void, env, i32)
> +DEF_HELPER_2(xscmpuqp, void, env, i32)
>  DEF_HELPER_2(xsmaxdp, void, env, i32)
>  DEF_HELPER_2(xsmindp, void, env, i32)
>  DEF_HELPER_2(xscvdpsp, void, env, i32)
> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
> index 5206258..ed9588e 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -628,6 +628,8 @@ GEN_VSX_HELPER_2(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300)
>  GEN_VSX_HELPER_2(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300)
>  GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
>  GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
> +GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
> +GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
>  GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
>  GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
>  GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
> diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
> index 2468ee9..7f09527 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -126,6 +126,8 @@ GEN_XX3FORM(xscmpexpdp, 0x0C, 0x07, PPC2_ISA300),
>  GEN_VSX_XFORM_300(xscmpexpqp, 0x04, 0x05, 0x00600001),
>  GEN_XX2IFORM(xscmpodp,  0x0C, 0x05, PPC2_VSX),
>  GEN_XX2IFORM(xscmpudp,  0x0C, 0x04, PPC2_VSX),
> +GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
> +GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
>  GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
>  GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
>  GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),