| Message ID | 1473662506-27441-18-git-send-email-nikunj@linux.vnet.ibm.com |
|---|---|
| State | New |
| Headers | show |
On Mon, Sep 12, 2016 at 12:11:46PM +0530, Nikunj A Dadhania wrote: > stxvb16x: Store VSX Vector Byte*16 > stxvh8x: Store VSX Vector Halfword*8 > > Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Basically the same comments as on the load side - this looks bogus to me. I think it would make sense to fold together the corresponding load and store patches - makes it easier to review that they're doing matching things. > --- > target-ppc/translate/vsx-impl.inc.c | 55 +++++++++++++++++++++++++++++++++++++ > target-ppc/translate/vsx-ops.inc.c | 2 ++ > 2 files changed, 57 insertions(+) > > diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c > index f2fc5f9..20afe3b 100644 > --- a/target-ppc/translate/vsx-impl.inc.c > +++ b/target-ppc/translate/vsx-impl.inc.c > @@ -165,6 +165,61 @@ static void gen_lxvh8x(DisasContext *ctx) > tcg_temp_free(EA); > } > > +static void gen_stxvb16x(DisasContext *ctx) > +{ > + TCGv_i64 xsh = cpu_vsrh(xS(ctx->opcode)); > + TCGv_i64 xsl = cpu_vsrl(xS(ctx->opcode)); > + TCGv EA; > + > + if (unlikely(!ctx->vsx_enabled)) { > + gen_exception(ctx, POWERPC_EXCP_VSXU); > + return; > + } > + gen_set_access_type(ctx, ACCESS_INT); > + EA = tcg_temp_new(); > + gen_addr_reg_index(ctx, EA); > + > + if (ctx->le_mode) { > + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ); > + tcg_gen_addi_tl(EA, EA, 8); > + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); > + } else { > + gen_helper_bswap32x2(xsh, xsh); > + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_LEQ); > + tcg_gen_addi_tl(EA, EA, 8); > + gen_helper_bswap32x2(xsl, xsl); > + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_LEQ); > + } > + tcg_temp_free(EA); > +} > + > +static void gen_stxvh8x(DisasContext *ctx) > +{ > + TCGv_i64 xsh = cpu_vsrh(xS(ctx->opcode)); > + TCGv_i64 xsl = cpu_vsrl(xS(ctx->opcode)); > + TCGv EA; > + > + if (unlikely(!ctx->vsx_enabled)) { > + gen_exception(ctx, POWERPC_EXCP_VSXU); > + return; > + } > + gen_set_access_type(ctx, ACCESS_INT); > + EA = tcg_temp_new(); > + gen_addr_reg_index(ctx, EA); > + if (ctx->le_mode) { > + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ); > + tcg_gen_addi_tl(EA, EA, 8); > + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); > + } else { > + gen_helper_bswap32x2(xsh, xsh); > + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_LEQ); > + tcg_gen_addi_tl(EA, EA, 8); > + gen_helper_bswap32x2(xsl, xsl); > + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_LEQ); > + } > + tcg_temp_free(EA); > +} > + > #define VSX_STORE_SCALAR(name, operation) \ > static void gen_##name(DisasContext *ctx) \ > { \ > diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c > index 598b349..f5afa0f 100644 > --- a/target-ppc/translate/vsx-ops.inc.c > +++ b/target-ppc/translate/vsx-ops.inc.c > @@ -17,6 +17,8 @@ GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207), > GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207), > GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), > GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX), > +GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300), > +GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300), > > GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207), > GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
David Gibson <david@gibson.dropbear.id.au> writes: > [ Unknown signature status ] > On Mon, Sep 12, 2016 at 12:11:46PM +0530, Nikunj A Dadhania wrote: >> stxvb16x: Store VSX Vector Byte*16 >> stxvh8x: Store VSX Vector Halfword*8 >> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> > > Basically the same comments as on the load side - this looks bogus to > me. > > I think it would make sense to fold together the corresponding load > and store patches - makes it easier to review that they're doing > matching things. Sure, I will fold store/load together. Regards Nikunj
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c index f2fc5f9..20afe3b 100644 --- a/target-ppc/translate/vsx-impl.inc.c +++ b/target-ppc/translate/vsx-impl.inc.c @@ -165,6 +165,61 @@ static void gen_lxvh8x(DisasContext *ctx) tcg_temp_free(EA); } +static void gen_stxvb16x(DisasContext *ctx) +{ + TCGv_i64 xsh = cpu_vsrh(xS(ctx->opcode)); + TCGv_i64 xsl = cpu_vsrl(xS(ctx->opcode)); + TCGv EA; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + + if (ctx->le_mode) { + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); + } else { + gen_helper_bswap32x2(xsh, xsh); + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_LEQ); + tcg_gen_addi_tl(EA, EA, 8); + gen_helper_bswap32x2(xsl, xsl); + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_LEQ); + } + tcg_temp_free(EA); +} + +static void gen_stxvh8x(DisasContext *ctx) +{ + TCGv_i64 xsh = cpu_vsrh(xS(ctx->opcode)); + TCGv_i64 xsl = cpu_vsrl(xS(ctx->opcode)); + TCGv EA; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + if (ctx->le_mode) { + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); + } else { + gen_helper_bswap32x2(xsh, xsh); + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_LEQ); + tcg_gen_addi_tl(EA, EA, 8); + gen_helper_bswap32x2(xsl, xsl); + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_LEQ); + } + tcg_temp_free(EA); +} + #define VSX_STORE_SCALAR(name, operation) \ static void gen_##name(DisasContext *ctx) \ { \ diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c index 598b349..f5afa0f 100644 --- a/target-ppc/translate/vsx-ops.inc.c +++ b/target-ppc/translate/vsx-ops.inc.c @@ -17,6 +17,8 @@ GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207), GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207), GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX), +GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207), GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
stxvb16x: Store VSX Vector Byte*16 stxvh8x: Store VSX Vector Halfword*8 Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> --- target-ppc/translate/vsx-impl.inc.c | 55 +++++++++++++++++++++++++++++++++++++ target-ppc/translate/vsx-ops.inc.c | 2 ++ 2 files changed, 57 insertions(+)