From patchwork Tue Jul 26 22:21:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 652992 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rzYHg2Drvz9t0p for ; Wed, 27 Jul 2016 08:50:39 +1000 (AEST) Received: from localhost ([::1]:42805 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bSBBN-00025o-1F for incoming@patchwork.ozlabs.org; Tue, 26 Jul 2016 18:50:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50089) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bSAl7-0001tt-Fl for qemu-devel@nongnu.org; Tue, 26 Jul 2016 18:23:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bSAl5-0000am-GA for qemu-devel@nongnu.org; Tue, 26 Jul 2016 18:23:28 -0400 Received: from gate.crashing.org ([63.228.1.57]:47478) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bSAl5-0000aH-6R; Tue, 26 Jul 2016 18:23:27 -0400 Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id u6QMLwGI007480; Tue, 26 Jul 2016 17:23:06 -0500 From: Benjamin Herrenschmidt To: qemu-ppc@nongnu.org Date: Wed, 27 Jul 2016 08:21:18 +1000 Message-Id: <1469571686-7284-24-git-send-email-benh@kernel.crashing.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1469571686-7284-1-git-send-email-benh@kernel.crashing.org> References: <1469571686-7284-1-git-send-email-benh@kernel.crashing.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 63.228.1.57 Subject: [Qemu-devel] [PATCH 24/32] ppc: Make alignment exceptions suck less X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The current alignment exception generation tries to load the opcode to put in DSISR from a context where a cpu_ldl_code() is really not a good idea. It might fault and longjmp out and that's not something we want happening here. Instead, pass the releavant opcode bits via the error_code. There are a couple of cases of alignment interrupts that won't set anything, the ones coming from access to direct store segments, but that doesn't happen in practice, nobody used direct store segments and they are gone from newer chips. Signed-off-by: Benjamin Herrenschmidt --- target-ppc/excp_helper.c | 9 +++++---- target-ppc/translate.c | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index c31bbad..9a26578 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -260,11 +260,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) } break; case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* XXX: this is false */ /* Get rS/rD and rA from faulting opcode */ - /* Broken for LE mode */ - env->spr[SPR_DSISR] |= (cpu_ldl_code(env, env->nip) - & 0x03FF0000) >> 16; + /* Note: the opcode fields will not be set properly for a direct + * store load/store, but nobody cares as nobody actually uses + * direct store segments. + */ + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index ddfec33..9af3f5f 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2202,7 +2202,7 @@ static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) tcg_gen_andi_tl(t0, EA, mask); tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); - t2 = tcg_const_i32(0); + t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); gen_update_nip(ctx, ctx->nip - 4); gen_helper_raise_exception_err(cpu_env, t1, t2); tcg_temp_free_i32(t1);