| Message ID | 1468346602-20700-3-git-send-email-nikunj@linux.vnet.ibm.com |
|---|---|
| State | New |
| Headers | show |
On Tue, Jul 12, 2016 at 11:33:18PM +0530, Nikunj A Dadhania wrote: > This flag will be used for POWER9 instructions. > > Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > target-ppc/cpu.h | 5 ++++- > target-ppc/translate_init.c | 2 +- > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 2666a3f..f48ff0f 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -2093,6 +2093,8 @@ enum { > PPC2_TM = 0x0000000000020000ULL, > /* Server PM instructgions (ISA 2.06, Book III) */ > PPC2_PM_ISA206 = 0x0000000000040000ULL, > + /* POWER ISA 3.0 */ > + PPC2_ISA300 = 0x0000000000080000ULL, > > #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ > PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ > @@ -2100,7 +2102,8 @@ enum { > PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ > PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ > PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ > - PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206) > + PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ > + PPC2_ISA300) > }; > > /*****************************************************************************/ > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 51bab23..9852524 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -8820,7 +8820,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) > PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | > PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | > PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | > - PPC2_TM | PPC2_PM_ISA206; > + PPC2_TM | PPC2_PM_ISA206 | PPC2_ISA300; > pcc->msr_mask = (1ull << MSR_SF) | > (1ull << MSR_TM) | > (1ull << MSR_VR) |
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 2666a3f..f48ff0f 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2093,6 +2093,8 @@ enum { PPC2_TM = 0x0000000000020000ULL, /* Server PM instructgions (ISA 2.06, Book III) */ PPC2_PM_ISA206 = 0x0000000000040000ULL, + /* POWER ISA 3.0 */ + PPC2_ISA300 = 0x0000000000080000ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ @@ -2100,7 +2102,8 @@ enum { PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ - PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206) + PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ + PPC2_ISA300) }; /*****************************************************************************/ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 51bab23..9852524 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8820,7 +8820,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_TM | PPC2_PM_ISA206; + PPC2_TM | PPC2_PM_ISA206 | PPC2_ISA300; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_TM) | (1ull << MSR_VR) |
This flag will be used for POWER9 instructions. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> --- target-ppc/cpu.h | 5 ++++- target-ppc/translate_init.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-)