From patchwork Tue Jul 12 11:14:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 647336 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rpfgJ1821z9s9Z for ; Tue, 12 Jul 2016 21:21:48 +1000 (AEST) Received: from localhost ([::1]:39053 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMvl3-0003ju-OI for incoming@patchwork.ozlabs.org; Tue, 12 Jul 2016 07:21:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48096) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMvfa-0006P2-JG for qemu-devel@nongnu.org; Tue, 12 Jul 2016 07:16:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bMvfU-00026U-UO for qemu-devel@nongnu.org; Tue, 12 Jul 2016 07:16:05 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:40827) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMvfU-00026A-Nl for qemu-devel@nongnu.org; Tue, 12 Jul 2016 07:16:00 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id A97D26C6A4F25 for ; Tue, 12 Jul 2016 12:15:46 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Tue, 12 Jul 2016 12:15:49 +0100 From: Leon Alrae To: Date: Tue, 12 Jul 2016 12:14:56 +0100 Message-ID: <1468322097-2315-11-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1468322097-2315-1-git-send-email-leon.alrae@imgtec.com> References: <1468322097-2315-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 10/11] target-mips: support CP0.Config4.AE bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Burton Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Paul Burton The read-only Config4.AE bit set denotes extended 10 bits ASID. Signed-off-by: Paul Burton Signed-off-by: James Hogan Signed-off-by: Leon Alrae --- target-mips/cpu.h | 1 + target-mips/translate.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 3e233ad..2c45839 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -468,6 +468,7 @@ struct CPUMIPSState { int32_t CP0_Config4_rw_bitmask; #define CP0C4_M 31 #define CP0C4_IE 29 +#define CP0C4_AE 28 #define CP0C4_KScrExist 16 #define CP0C4_MMUExtDef 14 #define CP0C4_FTLBPageSize 8 diff --git a/target-mips/translate.c b/target-mips/translate.c index 01510b3..bab52cb 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -20302,7 +20302,8 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { env->CP0_CMGCRBase = 0x1fbf8000 >> 4; } - env->CP0_EntryHi_ASID_mask = 0xff; + env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ? + 0x3ff : 0xff; env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); /* vectored interrupts not implemented, timer on int 7, no performance counters. */