From patchwork Mon Jun 27 10:11:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 640921 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rdPrk2Lgjz9t1K for ; Mon, 27 Jun 2016 20:12:54 +1000 (AEST) Received: from localhost ([::1]:57702 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHTXA-0008JP-8i for incoming@patchwork.ozlabs.org; Mon, 27 Jun 2016 06:12:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43917) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHTWE-0007i5-5L for qemu-devel@nongnu.org; Mon, 27 Jun 2016 06:11:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHTW9-0003wR-VQ for qemu-devel@nongnu.org; Mon, 27 Jun 2016 06:11:53 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:6891) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHTW9-0003wM-P4 for qemu-devel@nongnu.org; Mon, 27 Jun 2016 06:11:49 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 83996DC6D8164; Mon, 27 Jun 2016 11:11:45 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 27 Jun 2016 11:11:47 +0100 From: Leon Alrae To: Date: Mon, 27 Jun 2016 11:11:39 +0100 Message-ID: <1467022299-8509-1-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH] target-mips: replace MIPS64R6-generic with the real I6400 CPU model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" MIPS64R6-generic gradually gets closer to I6400 CPU, feature-wise. Rename it to make it clear which MIPS processor it is supposed to emulate. Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index b10284c..c43bdb7 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -671,26 +671,23 @@ static const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { - /* A generic CPU supporting MIPS64 Release 6 ISA. - FIXME: Support IEEE 754-2008 FP. - Eventually this should be replaced by a real CPU model. */ - .name = "MIPS64R6-generic", - .CP0_PRid = 0x00010000, + .name = "I6400", + .CP0_PRid = 0x1A900, .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | - (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | - (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | - (1 << CP0C3_RXI) | (1 << CP0C3_LPA), + (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | (0xfc << CP0C4_KScrExist), .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | - (1 << CP0C5_LLB), + (1 << CP0C5_LLB) | (1 << CP0C5_MRP), .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), .CP0_LLAddr_rw_bitmask = 0, @@ -703,9 +700,10 @@ static const mips_def_t mips_defs[] = .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | - (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), + (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), .CP1_fcr31_rw_bitmask = 0x0103FFFF, + .MSAIR = 0x03 << MSAIR_ProcID, .SEGBITS = 48, .PABITS = 48, .insn_flags = CPU_MIPS64R6 | ASE_MSA,