From patchwork Wed Mar 30 08:49:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 603263 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qZhN95zy6z9s6r for ; Wed, 30 Mar 2016 19:56:57 +1100 (AEDT) Received: from localhost ([::1]:52585 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBvs-00063E-4X for incoming@patchwork.ozlabs.org; Wed, 30 Mar 2016 04:56:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpn-0002k6-C8 for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1alBpl-0001ou-7P for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:39 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:49986) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpk-0001oh-V0 for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:37 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id C561F55D066C4 for ; Wed, 30 Mar 2016 09:50:32 +0100 (IST) Received: from lalrae-linux.kl.imgtec.org (192.168.169.37) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 30 Mar 2016 09:50:34 +0100 From: Leon Alrae To: Date: Wed, 30 Mar 2016 09:49:47 +0100 Message-ID: <1459327802-5102-7-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> References: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.169.37] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL v2 06/21] hw/mips/cps: create CPC block inside CPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Create Cluster Power Controller and add a link to the CPC MemoryRegion in GCR. Guest can enable / map CPC to any physical address by writing to the memory-mapped GCR_CPC_BASE register. Set vp-start-reset property to 1 to allow only first VP to run from reset. Others are brought up by the guest via CPC memory-mapped registers. Signed-off-by: Leon Alrae --- hw/mips/cps.c | 16 +++++++++++++ hw/misc/mips_cmgcr.c | 53 ++++++++++++++++++++++++++++++++++++++++++++ include/hw/mips/cps.h | 2 ++ include/hw/misc/mips_cmgcr.h | 10 +++++++++ 4 files changed, 81 insertions(+) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index e77b1da..d46547c 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -82,6 +82,21 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) cpu = MIPS_CPU(first_cpu); env = &cpu->env; + /* Cluster Power Controller */ + object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC); + qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default()); + + object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err); + object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err); + object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion(&s->container, 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); + /* Global Configuration Registers */ gcr_base = env->CP0_CMGCRBase << 4; @@ -91,6 +106,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err); object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err); object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err); + object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err); object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c index 4c93a133..37be239 100644 --- a/hw/misc/mips_cmgcr.c +++ b/hw/misc/mips_cmgcr.c @@ -15,6 +15,25 @@ #include "hw/sysbus.h" #include "sysemu/sysemu.h" #include "hw/misc/mips_cmgcr.h" +#include "hw/misc/mips_cpc.h" + +static inline bool is_cpc_connected(MIPSGCRState *s) +{ + return s->cpc_mr != NULL; +} + +static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val) +{ + if (is_cpc_connected(gcr)) { + gcr->cpc_base = val & GCR_CPC_BASE_MSK; + memory_region_transaction_begin(); + memory_region_set_address(gcr->cpc_mr, + gcr->cpc_base & GCR_CPC_BASE_CPCBASE_MSK); + memory_region_set_enabled(gcr->cpc_mr, + gcr->cpc_base & GCR_CPC_BASE_CPCEN_MSK); + memory_region_transaction_commit(); + } +} /* Read GCR registers */ static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size) @@ -30,6 +49,10 @@ static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size) return gcr->gcr_base; case GCR_REV_OFS: return gcr->gcr_rev; + case GCR_CPC_BASE_OFS: + return gcr->cpc_base; + case GCR_CPC_STATUS_OFS: + return is_cpc_connected(gcr); case GCR_L2_CONFIG_OFS: /* L2 BYPASS */ return GCR_L2_CONFIG_BYPASS_MSK; @@ -51,7 +74,12 @@ static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size) /* Write GCR registers */ static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { + MIPSGCRState *gcr = (MIPSGCRState *)opaque; + switch (addr) { + case GCR_CPC_BASE_OFS: + update_cpc_base(gcr, data); + break; default: qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" HWADDR_PRIx " 0x%" PRIx64 "\n", size, addr, data); @@ -73,11 +101,34 @@ static void mips_gcr_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); MIPSGCRState *s = MIPS_GCR(obj); + object_property_add_link(obj, "cpc", TYPE_MEMORY_REGION, + (Object **)&s->cpc_mr, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + &error_abort); + memory_region_init_io(&s->iomem, OBJECT(s), &gcr_ops, s, "mips-gcr", GCR_ADDRSPACE_SZ); sysbus_init_mmio(sbd, &s->iomem); } +static void mips_gcr_reset(DeviceState *dev) +{ + MIPSGCRState *s = MIPS_GCR(dev); + + update_cpc_base(s, 0); +} + +static const VMStateDescription vmstate_mips_gcr = { + .name = "mips-gcr", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT64(cpc_base, MIPSGCRState), + VMSTATE_END_OF_LIST() + }, +}; + static Property mips_gcr_properties[] = { DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1), DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800), @@ -89,6 +140,8 @@ static void mips_gcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->props = mips_gcr_properties; + dc->vmsd = &vmstate_mips_gcr; + dc->reset = mips_gcr_reset; } static const TypeInfo mips_gcr_info = { diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 1b200d6..88be765 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -22,6 +22,7 @@ #include "hw/sysbus.h" #include "hw/misc/mips_cmgcr.h" +#include "hw/misc/mips_cpc.h" #define TYPE_MIPS_CPS "mips-cps" #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS) @@ -35,6 +36,7 @@ typedef struct MIPSCPSState { MemoryRegion container; MIPSGCRState gcr; + MIPSCPCState cpc; } MIPSCPSState; qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number); diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h index 69403c3..cc60eef 100644 --- a/include/hw/misc/mips_cmgcr.h +++ b/include/hw/misc/mips_cmgcr.h @@ -26,6 +26,8 @@ #define GCR_CONFIG_OFS 0x0000 #define GCR_BASE_OFS 0x0008 #define GCR_REV_OFS 0x0030 +#define GCR_CPC_BASE_OFS 0x0088 +#define GCR_CPC_STATUS_OFS 0x00F0 #define GCR_L2_CONFIG_OFS 0x0130 /* Core Local and Core Other Block Register Map */ @@ -36,6 +38,11 @@ #define GCR_L2_CONFIG_BYPASS_SHF 20 #define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF) +/* GCR_CPC_BASE register fields */ +#define GCR_CPC_BASE_CPCEN_MSK 1 +#define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL +#define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK) + typedef struct MIPSGCRState MIPSGCRState; struct MIPSGCRState { SysBusDevice parent_obj; @@ -44,6 +51,9 @@ struct MIPSGCRState { int32_t num_vps; hwaddr gcr_base; MemoryRegion iomem; + MemoryRegion *cpc_mr; + + uint64_t cpc_base; }; #endif /* _MIPS_GCR_H */