From patchwork Thu Oct 22 16:22:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 534479 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7B159141312 for ; Fri, 23 Oct 2015 03:23:37 +1100 (AEDT) Received: from localhost ([::1]:33116 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZpIeM-0003L9-UG for incoming@patchwork.ozlabs.org; Thu, 22 Oct 2015 12:23:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41413) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZpIdi-0002D1-Uj for qemu-devel@nongnu.org; Thu, 22 Oct 2015 12:22:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZpIdd-0004IC-Ky for qemu-devel@nongnu.org; Thu, 22 Oct 2015 12:22:54 -0400 Received: from mx2.suse.de ([195.135.220.15]:48702) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZpIdd-0004Hr-Ef for qemu-devel@nongnu.org; Thu, 22 Oct 2015 12:22:49 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 27594AC30; Thu, 22 Oct 2015 16:22:47 +0000 (UTC) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Thu, 22 Oct 2015 18:22:35 +0200 Message-Id: <1445530959-19309-5-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1445530959-19309-1-git-send-email-afaerber@suse.de> References: <1445530959-19309-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 195.135.220.15 Cc: Blue Swirl , Peter Crosthwaite , Mark Cave-Ayland , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Peter Crosthwaite Subject: [Qemu-devel] [PULL 4/8] disas: QOMify sparc specific disas setup X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite Move the target_disas() sparc specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c. Cc: Mark Cave-Ayland Signed-off-by: Peter Crosthwaite Signed-off-by: Andreas Färber --- disas.c | 10 ---------- target-sparc/cpu.c | 9 +++++++++ 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/disas.c b/disas.c index 1ef2596..5b3acf0 100644 --- a/disas.c +++ b/disas.c @@ -214,11 +214,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code, s.info.mach = bfd_mach_i386_i386; } s.info.print_insn = print_insn_i386; -#elif defined(TARGET_SPARC) - s.info.print_insn = print_insn_sparc; -#ifdef TARGET_SPARC64 - s.info.mach = bfd_mach_sparc_v9b; -#endif #elif defined(TARGET_PPC) if ((flags >> 16) & 1) { s.info.endian = BFD_ENDIAN_LITTLE; @@ -423,11 +418,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu, s.info.print_insn = print_insn_i386; #elif defined(TARGET_ALPHA) s.info.print_insn = print_insn_alpha; -#elif defined(TARGET_SPARC) - s.info.print_insn = print_insn_sparc; -#ifdef TARGET_SPARC64 - s.info.mach = bfd_mach_sparc_v9b; -#endif #elif defined(TARGET_PPC) if (flags & 0xFFFF) { /* If we have a precise definition of the instruction set, use it. */ diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 82bb72a..d98682b 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -90,6 +90,14 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } +static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) +{ + info->print_insn = print_insn_sparc; +#ifdef TARGET_SPARC64 + info->mach = bfd_mach_sparc_v9b; +#endif +} + static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model) { CPUClass *cc = CPU_GET_CLASS(cpu); @@ -848,6 +856,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->do_unaligned_access = sparc_cpu_do_unaligned_access; cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; #endif + cc->disas_set_info = cpu_sparc_disas_set_info; #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) cc->gdb_num_core_regs = 86;