diff mbox

target-mips: add missing restriction in DAUI instruction

Message ID 1442234994-15841-1-git-send-email-leon.alrae@imgtec.com
State New
Headers show

Commit Message

Leon Alrae Sept. 14, 2015, 12:49 p.m. UTC 
rs cannot be the zero register, Reserved Instruction exception must be
signalled for this case.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/translate.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Aurelien Jarno Sept. 14, 2015, 7:19 p.m. UTC | #1 
On 2015-09-14 13:49, Leon Alrae wrote:
> rs cannot be the zero register, Reserved Instruction exception must be
> signalled for this case.
> 
> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
> ---
>  target-mips/translate.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 7fb7c01..a8fd4a3 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -19512,7 +19512,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
>  #if defined(TARGET_MIPS64)
>              /* OPC_DAUI */
>              check_mips_64(ctx);
> -            if (rt != 0) {
> +            if (rs == 0) {
> +                generate_exception(ctx, EXCP_RI);
> +            } else if (rt != 0) {
>                  TCGv t0 = tcg_temp_new();
>                  gen_load_gpr(t0, rs);
>                  tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
diff mbox

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 7fb7c01..a8fd4a3 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19512,7 +19512,9 @@  static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
 #if defined(TARGET_MIPS64)
             /* OPC_DAUI */
             check_mips_64(ctx);
-            if (rt != 0) {
+            if (rs == 0) {
+                generate_exception(ctx, EXCP_RI);
+            } else if (rt != 0) {
                 TCGv t0 = tcg_temp_new();
                 gen_load_gpr(t0, rs);
                 tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);