From patchwork Mon Aug 17 19:38:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 508076 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7572C140134 for ; Tue, 18 Aug 2015 05:49:47 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=lYYHxumu; dkim-atps=neutral Received: from localhost ([::1]:58141 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZRQPh-0004F0-CS for incoming@patchwork.ozlabs.org; Mon, 17 Aug 2015 15:49:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZRQG0-00066L-Bq for qemu-devel@nongnu.org; Mon, 17 Aug 2015 15:39:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZRQFx-0008KR-GA for qemu-devel@nongnu.org; Mon, 17 Aug 2015 15:39:44 -0400 Received: from mail-qg0-x233.google.com ([2607:f8b0:400d:c04::233]:36600) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZRQFx-0008KL-Bw for qemu-devel@nongnu.org; Mon, 17 Aug 2015 15:39:41 -0400 Received: by qgdd90 with SMTP id d90so101565346qgd.3 for ; Mon, 17 Aug 2015 12:39:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=FzrZ9qq/b8Fp/+aFTSKYygOZgtcYELmsKrvesfMOuRg=; b=lYYHxumuZBdP9HzbsfL7f826AIdfYQFTKfuMpcs89yr07Cky5A+s5diRs/2SAQF+O0 f3QyjjYJK4oSR/i/kgCerJ+n2nE1bwWYXO2uuxwE90juiApGkm2HX0QYutaUw/umYdKc K2HITg1INJuD7ZUis5xQHXPc30dzfmHkvKmaplLbzyq9guY1h7Pee7zqe3KJ9p17Yitp 3ZMxFdSu1rM+x0mwAH0/6PyheXwsjj3RneopJZnf/0qMdv+3T80D0BIEznHwidQuiU8T pVltQEtn/AjUkVrcrz4Fig94gADm51w+Z7cmMq5Hs0LFIfo+4tcR1FQRbVNJvWvHyR1o sRfg== X-Received: by 10.140.94.42 with SMTP id f39mr5485471qge.29.1439840380972; Mon, 17 Aug 2015 12:39:40 -0700 (PDT) Received: from anchor.com (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by smtp.gmail.com with ESMTPSA id z101sm8772880qge.31.2015.08.17.12.39.39 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Aug 2015 12:39:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Aug 2015 12:38:34 -0700 Message-Id: <1439840320-20897-12-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1439840320-20897-1-git-send-email-rth@twiddle.net> References: <1439840320-20897-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c04::233 Cc: peter.maydell@linaro.org, Aurelien Jarno Subject: [Qemu-devel] [PATCH 11/17] tcg: update README about size changing ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Aurelien Jarno Cc: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/README | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/tcg/README b/tcg/README index 61b3899..a22f251 100644 --- a/tcg/README +++ b/tcg/README @@ -466,13 +466,25 @@ On a 32 bit target, all 64 bit operations are converted to 32 bits. A few specific operations must be implemented to allow it (see add2_i32, sub2_i32, brcond2_i32). +On a 64 bit target, the values are transfered between 32 and 64-bit +registers using the following ops: +- trunc_shr_i64_i32 +- ext_i32_i64 +- extu_i32_i64 + +They ensure that the values are correctly truncated or extended when +moved from a 32-bit to a 64-bit register or vice-versa. Note that the +trunc_shr_i64_i32 is an optional op. It is not necessary to implement +it if all the following conditions are met: +- 64-bit registers can hold 32-bit values +- 32-bit values in a 64-bit register do not need to stay zero or + sign extended +- all 32-bit TCG ops ignore the high part of 64-bit registers + Floating point operations are not supported in this version. A previous incarnation of the code generator had full support of them, but it is better to concentrate on integer operations first. -On a 64 bit target, no assumption is made in TCG about the storage of -the 32 bit values in 64 bit registers. - 4.2) Constraints GCC like constraints are used to define the constraints of every