From patchwork Fri Aug 14 14:59:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 507444 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D212C1401E7 for ; Sat, 15 Aug 2015 01:08:06 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=gsdNGRxs; dkim-atps=neutral Received: from localhost ([::1]:46736 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZQGaS-0005Lb-T4 for incoming@patchwork.ozlabs.org; Fri, 14 Aug 2015 11:08:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52716) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZQGSu-0007ve-HG for qemu-devel@nongnu.org; Fri, 14 Aug 2015 11:00:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZQGSt-0006g1-7k for qemu-devel@nongnu.org; Fri, 14 Aug 2015 11:00:16 -0400 Received: from mail-qk0-x229.google.com ([2607:f8b0:400d:c09::229]:34752) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZQGSt-0006fc-3b for qemu-devel@nongnu.org; Fri, 14 Aug 2015 11:00:15 -0400 Received: by qkcs67 with SMTP id s67so26428445qkc.1 for ; Fri, 14 Aug 2015 08:00:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=STgwfR2bpE7BKfal+NYIo8iMrmfF8b/2sTT5EJ/9jHQ=; b=gsdNGRxswpmj68j4kuOCkAF8fNFg2VIGmE7jr8tHvJXSS/Il4Ra6cYQCACvaGnbpTh gFFodr/4j4ocprGloKXrRliO6bzP4LEeedaspN3xTqAogHP10f6exlt11e7XrRUwQa5w kU76I4JUaRA3waakRN1RmVFDnm9VA9yr6IT77m5ns1+G4NsPCaBGSBsZOGyL88lhOEe3 H6Bb8PjCbVEROoN2l6pGp8J+NwMP9rHB6qY1MNFilDDjICEyUUn4EDCjpYOdEs2lUxCI w5xWAlPu09XKnjG8O/R7ZvulZX9zwB/JM3OEmVW7d14YVXwaiwEEhaU8XihE+jsoVej1 IF2w== X-Received: by 10.55.23.136 with SMTP id 8mr80841008qkx.43.1439564414654; Fri, 14 Aug 2015 08:00:14 -0700 (PDT) Received: from anchor.com (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by smtp.gmail.com with ESMTPSA id k6sm3128640qhk.2.2015.08.14.08.00.13 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2015 08:00:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Aug 2015 07:59:25 -0700 Message-Id: <1439564366-11633-11-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1439564366-11633-1-git-send-email-rth@twiddle.net> References: <1439564366-11633-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c09::229 Cc: peter.maydell@linaro.org, schwab@linux-m68k.org, laurent@vivier.eu, gerg@uclinux.org Subject: [Qemu-devel] [PATCH 10/11] target-m68k: Inline shifts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-m68k/helper.c | 52 --------------------------- target-m68k/helper.h | 3 -- target-m68k/translate.c | 94 +++++++++++++++++++++++++++++++++++++------------ 3 files changed, 72 insertions(+), 77 deletions(-) diff --git a/target-m68k/helper.c b/target-m68k/helper.c index ff7e481..6bd80a5 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -322,58 +322,6 @@ void HELPER(set_sr)(CPUM68KState *env, uint32_t val) m68k_switch_sp(env); } -uint32_t HELPER(shl_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) -{ - uint64_t result; - - shift &= 63; - result = (uint64_t)val << shift; - - env->cc_c = (result >> 32) & 1; - env->cc_n = result; - env->cc_z = result; - env->cc_v = 0; - env->cc_x = shift ? env->cc_c : env->cc_x; - - return result; -} - -uint32_t HELPER(shr_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) -{ - uint64_t temp; - uint32_t result; - - shift &= 63; - temp = (uint64_t)val << 32 >> shift; - result = temp >> 32; - - env->cc_c = (temp >> 31) & 1; - env->cc_n = result; - env->cc_z = result; - env->cc_v = 0; - env->cc_x = shift ? env->cc_c : env->cc_x; - - return result; -} - -uint32_t HELPER(sar_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) -{ - uint64_t temp; - uint32_t result; - - shift &= 63; - temp = (int64_t)val << 32 >> shift; - result = temp >> 32; - - env->cc_c = (temp >> 31) & 1; - env->cc_n = result; - env->cc_z = result; - env->cc_v = result ^ val; - env->cc_x = shift ? env->cc_c : env->cc_x; - - return result; -} - /* FPU helpers. */ uint32_t HELPER(f64_to_i32)(CPUM68KState *env, float64 val) { diff --git a/target-m68k/helper.h b/target-m68k/helper.h index c868148..9985f9b 100644 --- a/target-m68k/helper.h +++ b/target-m68k/helper.h @@ -5,9 +5,6 @@ DEF_HELPER_2(divu, void, env, i32) DEF_HELPER_2(divs, void, env, i32) DEF_HELPER_3(addx_cc, i32, env, i32, i32) DEF_HELPER_3(subx_cc, i32, env, i32, i32) -DEF_HELPER_3(shl_cc, i32, env, i32, i32) -DEF_HELPER_3(shr_cc, i32, env, i32, i32) -DEF_HELPER_3(sar_cc, i32, env, i32, i32) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 19097c2..a536054 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2060,48 +2060,98 @@ DISAS_INSN(addx) gen_helper_addx_cc(reg, cpu_env, reg, src); } -/* TODO: This could be implemented without helper functions. */ DISAS_INSN(shift_im) { - TCGv reg; - int tmp; - TCGv shift; + TCGv reg = DREG(insn, 0); + int count = (insn >> 9) & 7; + int arith = insn & 8; - set_cc_op(s, CC_OP_FLAGS); + if (count == 0) { + count = 8; + } - reg = DREG(insn, 0); - tmp = (insn >> 9) & 7; - if (tmp == 0) - tmp = 8; - shift = tcg_const_i32(tmp); - /* No need to flush flags becuse we know we will set C flag. */ if (insn & 0x100) { - gen_helper_shl_cc(reg, cpu_env, reg, shift); + tcg_gen_shri_i32(QREG_CC_C, reg, 31 - count); + tcg_gen_shli_i32(QREG_CC_N, reg, count); } else { - if (insn & 8) { - gen_helper_shr_cc(reg, cpu_env, reg, shift); + tcg_gen_shri_i32(QREG_CC_C, reg, count - 1); + if (arith) { + tcg_gen_sari_i32(QREG_CC_N, reg, count); } else { - gen_helper_sar_cc(reg, cpu_env, reg, shift); + tcg_gen_shri_i32(QREG_CC_N, reg, count); } } + tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); + tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); + tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); + + /* Note that ColdFire always clears V, while M68000 sets it for + a change in the sign bit. */ + if (arith && m68k_feature(s->env, M68K_FEATURE_M68000)) { + tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg); + } else { + tcg_gen_movi_i32(QREG_CC_V, 0); + } + + tcg_gen_mov_i32(reg, QREG_CC_N); + set_cc_op(s, CC_OP_FLAGS); } DISAS_INSN(shift_reg) { - TCGv reg; - TCGv shift; + TCGv reg, s32; + TCGv_i64 t64, s64; + int arith = insn & 8; reg = DREG(insn, 0); - shift = DREG(insn, 9); + t64 = tcg_temp_new_i64(); + s64 = tcg_temp_new_i64(); + s32 = tcg_temp_new(); + + /* Note that m68k truncates the shift count modulo 64, not 32. + In addition, a 64-bit shift makes it easy to find "the last + bit shifted out", for the carry flag. */ + tcg_gen_andi_i32(s32, DREG(insn, 9), 63); + tcg_gen_extu_i32_i64(s64, s32); + + /* Non-arithmetic shift clears V. Use it as a source zero here. */ + tcg_gen_movi_i32(QREG_CC_V, 0); + if (insn & 0x100) { - gen_helper_shl_cc(reg, cpu_env, reg, shift); + tcg_gen_extu_i32_i64(t64, reg); + tcg_gen_shl_i64(t64, t64, s64); + tcg_temp_free_i64(s64); + tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64); + tcg_temp_free_i64(t64); + tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); } else { - if (insn & 8) { - gen_helper_shr_cc(reg, cpu_env, reg, shift); + tcg_gen_extu_i32_i64(t64, reg); + tcg_gen_shli_i64(t64, t64, 32); + if (arith) { + tcg_gen_sar_i64(t64, t64, s64); } else { - gen_helper_sar_cc(reg, cpu_env, reg, shift); + tcg_gen_shr_i64(t64, t64, s64); } + tcg_temp_free_i64(s64); + tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64); + tcg_temp_free_i64(t64); + tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31); } + tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); + + /* Note that X = C, but only if the shift count was non-zero. */ + tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, + QREG_CC_C, QREG_CC_X); + tcg_temp_free(s32); + + /* Note that ColdFire always clears V (which we have done above), + while M68000 sets it for a change in the sign bit. */ + if (arith && m68k_feature(s->env, M68K_FEATURE_M68000)) { + tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg); + } + + /* Write back the result. */ + tcg_gen_mov_i32(reg, QREG_CC_N); set_cc_op(s, CC_OP_FLAGS); }