diff mbox

[for-2.5,29/30] m68k: add rol/rox/ror/roxr

Message ID 1439151229-27747-30-git-send-email-laurent@vivier.eu
State New
Headers show

Commit Message

Laurent Vivier Aug. 9, 2015, 8:13 p.m. UTC 
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/helper.c    | 212 ++++++++++++++++++++++++++++++++++++++++++++++++
 target-m68k/helper.h    |  14 ++++
 target-m68k/translate.c | 207 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 433 insertions(+)

Comments

Richard Henderson Aug. 12, 2015, 7:40 p.m. UTC | #1 
On 08/09/2015 01:13 PM, Laurent Vivier wrote:
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
>  target-m68k/helper.c    | 212 ++++++++++++++++++++++++++++++++++++++++++++++++
>  target-m68k/helper.h    |  14 ++++
>  target-m68k/translate.c | 207 ++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 433 insertions(+)
> 
> diff --git a/target-m68k/helper.c b/target-m68k/helper.c
> index 16fca70..532f366 100644
> --- a/target-m68k/helper.c
> +++ b/target-m68k/helper.c
> @@ -25,6 +25,42 @@
>  
>  #define SIGNBIT (1u << 31)
>  
> +/* modulo 33 table */
> +const uint8_t rox32_table[64] = {
> +    0,  1,  2,  3,  4,  5,  6,  7,
> +    8,  9, 10, 11, 12, 13, 14, 15,
> +   16, 17, 18, 19, 20, 21, 22, 23,
> +   24, 25, 26, 27, 28, 29, 30, 31,
> +   32,  0,  1,  2,  3,  4,  5,  6,
> +    7,  8,  9, 10, 11, 12, 13, 14,
> +   15, 16, 17, 18, 19, 20, 21, 22,
> +   23, 24, 25, 26, 27, 28, 29, 30,
> +};
> +
> +/* modulo 17 table */
> +const uint8_t rox16_table[64] = {
> +    0,  1,  2,  3,  4,  5,  6,  7,
> +    8,  9, 10, 11, 12, 13, 14, 15,
> +   16,  0,  1,  2,  3,  4,  5,  6,
> +    7,  8,  9, 10, 11, 12, 13, 14,
> +   15, 16,  0,  1,  2,  3,  4,  5,
> +    6,  7,  8,  9, 10, 11, 12, 13,
> +   14, 15, 16,  0,  1, 2,   3,  4,
> +    5,  6,  7,  8,  9, 10, 11, 12,
> +};
> +
> +/* modulo 9 table */
> +const uint8_t rox8_table[64] = {
> +    0, 1, 2, 3, 4, 5, 6, 7,
> +    8, 0, 1, 2, 3, 4, 5, 6,
> +    7, 8, 0, 1, 2, 3, 4, 5,
> +    6, 7, 8, 0, 1, 2, 3, 4,
> +    5, 6, 7, 8, 0, 1, 2, 3,
> +    4, 5, 6, 7, 8, 0, 1, 2,
> +    3, 4, 5, 6, 7, 8, 0, 1,
> +    2, 3, 4, 5, 6, 7, 8, 0,
> +};

Why would you have these tables as opposed to just using the C modulo operator?

> +uint32_t HELPER(rol32)(uint32_t val, uint32_t shift)
> +{
> +    uint32_t result;
> +    if (shift == 0 || shift == 32) {
> +        return val;
> +    }
> +    result = (val << shift) | (val >> (32 - shift));
> +    return result;
> +}
> +
> +uint32_t HELPER(ror32)(uint32_t val, uint32_t shift)
> +{
> +    uint32_t result;
> +    if (shift == 0 || shift == 32) {
> +        return val;
> +    }
> +    result = (val >> shift) | (val << (32 - shift));
> +    return result;
> +}

Easily done in tcg directly.  But aren't these are actually unused?

> +#define HELPER_ROXR(type, bits) \
> +uint32_t HELPER(glue(glue(roxr, bits), _cc))(CPUM68KState *env, \
> +                                             uint32_t val, uint32_t shift) \
> +{ \

Again, I think perhaps a 64-bit shift type might help clean up these cases.
Start by forming the 34-bit quantity (X : VAL : 0); end by extracting bits
[32:1] as the result and bit 0 as X.

> +DISAS_INSN(rotate_im)
...
> +DISAS_INSN(rotate_reg)

Again, surely you can share code.


r~
diff mbox

Patch

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 16fca70..532f366 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -25,6 +25,42 @@ 
 
 #define SIGNBIT (1u << 31)
 
+/* modulo 33 table */
+const uint8_t rox32_table[64] = {
+    0,  1,  2,  3,  4,  5,  6,  7,
+    8,  9, 10, 11, 12, 13, 14, 15,
+   16, 17, 18, 19, 20, 21, 22, 23,
+   24, 25, 26, 27, 28, 29, 30, 31,
+   32,  0,  1,  2,  3,  4,  5,  6,
+    7,  8,  9, 10, 11, 12, 13, 14,
+   15, 16, 17, 18, 19, 20, 21, 22,
+   23, 24, 25, 26, 27, 28, 29, 30,
+};
+
+/* modulo 17 table */
+const uint8_t rox16_table[64] = {
+    0,  1,  2,  3,  4,  5,  6,  7,
+    8,  9, 10, 11, 12, 13, 14, 15,
+   16,  0,  1,  2,  3,  4,  5,  6,
+    7,  8,  9, 10, 11, 12, 13, 14,
+   15, 16,  0,  1,  2,  3,  4,  5,
+    6,  7,  8,  9, 10, 11, 12, 13,
+   14, 15, 16,  0,  1, 2,   3,  4,
+    5,  6,  7,  8,  9, 10, 11, 12,
+};
+
+/* modulo 9 table */
+const uint8_t rox8_table[64] = {
+    0, 1, 2, 3, 4, 5, 6, 7,
+    8, 0, 1, 2, 3, 4, 5, 6,
+    7, 8, 0, 1, 2, 3, 4, 5,
+    6, 7, 8, 0, 1, 2, 3, 4,
+    5, 6, 7, 8, 0, 1, 2, 3,
+    4, 5, 6, 7, 8, 0, 1, 2,
+    3, 4, 5, 6, 7, 8, 0, 1,
+    2, 3, 4, 5, 6, 7, 8, 0,
+};
+
 /* Sort alphabetically, except for "any". */
 static gint m68k_cpu_list_compare(gconstpointer a, gconstpointer b)
 {
@@ -411,6 +447,26 @@  uint32_t HELPER(ff1)(uint32_t x)
     return n;
 }
 
+uint32_t HELPER(rol32)(uint32_t val, uint32_t shift)
+{
+    uint32_t result;
+    if (shift == 0 || shift == 32) {
+        return val;
+    }
+    result = (val << shift) | (val >> (32 - shift));
+    return result;
+}
+
+uint32_t HELPER(ror32)(uint32_t val, uint32_t shift)
+{
+    uint32_t result;
+    if (shift == 0 || shift == 32) {
+        return val;
+    }
+    result = (val >> shift) | (val << (32 - shift));
+    return result;
+}
+
 uint32_t HELPER(sats)(uint32_t val, uint32_t ccr)
 {
     /* The result has the opposite sign to the original value.  */
@@ -634,6 +690,162 @@  HELPER_SAR(int8_t, 8)
 HELPER_SAR(int16_t, 16)
 HELPER_SAR(int32_t, 32)
 
+#define HELPER_ROL(type, bits) \
+uint32_t HELPER(glue(glue(rol, bits), _cc))(CPUM68KState *env, \
+                                            uint32_t val, uint32_t shift) \
+{ \
+    type result; \
+    uint32_t flags; \
+    int count = shift & (bits - 1); \
+    if (count) { \
+        result = ((type)val << count) | ((type)val >> (bits - count)); \
+    } else { \
+        result = (type)val; \
+    } \
+    flags = 0; \
+    if (result == 0) { \
+        flags |= CCF_Z; \
+    } \
+    if (result & (1 << (bits - 1))) { \
+        flags |= CCF_N; \
+    } \
+    if (shift && result & 1) { \
+        flags |= CCF_C; \
+    } \
+    env->cc_dest = flags; \
+    return result; \
+}
+
+HELPER_ROL(uint8_t, 8)
+HELPER_ROL(uint16_t, 16)
+HELPER_ROL(uint32_t, 32)
+
+#define HELPER_ROR(type, bits) \
+uint32_t HELPER(glue(glue(ror, bits), _cc))(CPUM68KState *env, \
+                                            uint32_t val, uint32_t shift) \
+{ \
+    type result; \
+    uint32_t flags; \
+    int count = shift & (bits - 1); \
+    if (count) { \
+        result = ((type)val >> count) | ((type)val << (bits - count)); \
+    } else { \
+        result = (type)val; \
+    } \
+    flags = 0; \
+    if (result == 0) { \
+        flags |= CCF_Z; \
+    } \
+    if (result & (1 << (bits - 1))) { \
+        flags |= CCF_N; \
+    } \
+    if (shift && result & (1 << (bits - 1))) { \
+        flags |= CCF_C; \
+    } \
+    env->cc_dest = flags; \
+    return result; \
+}
+
+HELPER_ROR(uint8_t, 8)
+HELPER_ROR(uint16_t, 16)
+HELPER_ROR(uint32_t, 32)
+
+#define HELPER_ROXR(type, bits) \
+uint32_t HELPER(glue(glue(roxr, bits), _cc))(CPUM68KState *env, \
+                                             uint32_t val, uint32_t shift) \
+{ \
+    type result; \
+    uint32_t flags; \
+    int count = shift; \
+    if (bits == 8) { \
+        count = rox8_table[count]; \
+    } \
+    if (bits == 16) { \
+        count = rox16_table[count]; \
+    } \
+    if (bits == 32) { \
+        count = rox32_table[count]; \
+    } \
+    if (count) { \
+        if (count == bits) { \
+            result = ((type)env->cc_x << (bits - count));\
+        } else { \
+            result = ((type)val >> count) | \
+                     ((type)env->cc_x << (bits - count));\
+        } \
+        if (count > 1) { \
+            result |= (type)val << (bits + 1 - count); \
+        } \
+        env->cc_x = ((type)val >> (count - 1)) & 1; \
+    } else { \
+        result = (type)val; \
+    } \
+    flags = 0; \
+    if (result == 0) { \
+        flags |= CCF_Z; \
+    } \
+    if (result & (1 << (bits - 1))) { \
+        flags |= CCF_N; \
+    } \
+    if (env->cc_x) { \
+        flags |= CCF_C; \
+    } \
+    env->cc_dest = flags; \
+    return result; \
+}
+
+HELPER_ROXR(uint8_t, 8)
+HELPER_ROXR(uint16_t, 16)
+HELPER_ROXR(uint32_t, 32)
+
+#define HELPER_ROXL(type, bits) \
+uint32_t HELPER(glue(glue(roxl, bits), _cc))(CPUM68KState *env, \
+                                             uint32_t val, uint32_t shift) \
+{ \
+    type result; \
+    uint32_t flags; \
+    int count; \
+    count = shift; \
+    if (bits == 8) { \
+        count = rox8_table[count]; \
+    } \
+    if (bits == 16) { \
+        count = rox16_table[count]; \
+    } \
+    if (bits == 32) { \
+        count = rox32_table[count]; \
+    } \
+    if (count) { \
+        if (count == bits) { \
+            result = ((type)env->cc_x << (count - 1)); \
+        } else { \
+            result = ((type)val << count) | ((type)env->cc_x << (count - 1)); \
+        } \
+        if (count > 1) { \
+            result |= (type)val >> (bits + 1 - count); \
+        } \
+        env->cc_x = ((type)val >> (bits - count)) & 1; \
+    } else { \
+        result = (type)val; \
+    } \
+    flags = 0; \
+    if (result == 0) { \
+        flags |= CCF_Z; \
+    } \
+    if (result & (1 << (bits - 1))) { \
+        flags |= CCF_N; \
+    } \
+    if (env->cc_x) { \
+        flags |= CCF_C; \
+    } \
+    env->cc_dest = flags; \
+    return result; \
+}
+
+HELPER_ROXL(uint8_t, 8)
+HELPER_ROXL(uint16_t, 16)
+HELPER_ROXL(uint32_t, 32)
+
 /* FPU helpers.  */
 uint32_t HELPER(f64_to_i32)(CPUM68KState *env, float64 val)
 {
diff --git a/target-m68k/helper.h b/target-m68k/helper.h
index a39ee7d..209064c 100644
--- a/target-m68k/helper.h
+++ b/target-m68k/helper.h
@@ -1,5 +1,7 @@ 
 DEF_HELPER_1(bitrev, i32, i32)
 DEF_HELPER_1(ff1, i32, i32)
+DEF_HELPER_2(rol32, i32, i32, i32)
+DEF_HELPER_2(ror32, i32, i32, i32)
 DEF_HELPER_2(sats, i32, i32, i32)
 DEF_HELPER_2(divu, void, env, i32)
 DEF_HELPER_2(divs, void, env, i32)
@@ -27,6 +29,18 @@  DEF_HELPER_3(sal32_cc, i32, env, i32, i32)
 DEF_HELPER_3(sar8_cc, i32, env, i32, i32)
 DEF_HELPER_3(sar16_cc, i32, env, i32, i32)
 DEF_HELPER_3(sar32_cc, i32, env, i32, i32)
+DEF_HELPER_3(rol8_cc, i32, env, i32, i32)
+DEF_HELPER_3(rol16_cc, i32, env, i32, i32)
+DEF_HELPER_3(rol32_cc, i32, env, i32, i32)
+DEF_HELPER_3(ror8_cc, i32, env, i32, i32)
+DEF_HELPER_3(ror16_cc, i32, env, i32, i32)
+DEF_HELPER_3(ror32_cc, i32, env, i32, i32)
+DEF_HELPER_3(roxr8_cc, i32, env, i32, i32)
+DEF_HELPER_3(roxr16_cc, i32, env, i32, i32)
+DEF_HELPER_3(roxr32_cc, i32, env, i32, i32)
+DEF_HELPER_3(roxl8_cc, i32, env, i32, i32)
+DEF_HELPER_3(roxl16_cc, i32, env, i32, i32)
+DEF_HELPER_3(roxl32_cc, i32, env, i32, i32)
 DEF_HELPER_2(xflag_lt_i8, i32, i32, i32)
 DEF_HELPER_2(xflag_lt_i16, i32, i32, i32)
 DEF_HELPER_2(xflag_lt_i32, i32, i32, i32)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 22d4296..5fc7a11 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2677,6 +2677,206 @@  DISAS_INSN(shift_mem)
     set_cc_op(s, CC_OP_SHIFTW);
 }
 
+DISAS_INSN(rotate_im)
+{
+    TCGv reg;
+    TCGv shift;
+    int tmp;
+
+    reg = DREG(insn, 0);
+    tmp = (insn >> 9) & 7;
+    if (tmp == 0) {
+        tmp = 8;
+    }
+    shift = tcg_const_i32(tmp);
+    if (insn & 8) {
+        if (insn & 0x100) {
+            gen_helper_rol32_cc(reg, cpu_env, reg, shift);
+        } else {
+            gen_helper_ror32_cc(reg, cpu_env, reg, shift);
+        }
+    } else {
+        if (insn & 0x100) {
+            gen_helper_roxl32_cc(reg, cpu_env, reg, shift);
+        } else {
+            gen_helper_roxr32_cc(reg, cpu_env, reg, shift);
+        }
+    }
+    set_cc_op(s, CC_OP_FLAGS);
+}
+
+DISAS_INSN(rotate8_im)
+{
+    TCGv reg;
+    TCGv dest;
+    TCGv shift;
+    int tmp;
+
+    reg = DREG(insn, 0);
+    tmp = (insn >> 9) & 7;
+    if (tmp == 0) {
+        tmp = 8;
+    }
+    dest = tcg_temp_new_i32();
+    shift = tcg_const_i32(tmp);
+    if (insn & 8) {
+        if (insn & 0x100) {
+            gen_helper_rol8_cc(dest, cpu_env, reg, shift);
+        } else {
+            gen_helper_ror8_cc(dest, cpu_env, reg, shift);
+        }
+    } else {
+        if (insn & 0x100) {
+            gen_helper_roxl8_cc(dest, cpu_env, reg, shift);
+        } else {
+            gen_helper_roxr8_cc(dest, cpu_env, reg, shift);
+        }
+    }
+    gen_partset_reg(OS_BYTE, reg, dest);
+    set_cc_op(s, CC_OP_FLAGS);
+}
+
+DISAS_INSN(rotate16_im)
+{
+    TCGv reg;
+    TCGv dest;
+    TCGv shift;
+    int tmp;
+
+    reg = DREG(insn, 0);
+    tmp = (insn >> 9) & 7;
+    if (tmp == 0) {
+        tmp = 8;
+    }
+    dest = tcg_temp_new_i32();
+    shift = tcg_const_i32(tmp);
+    if (insn & 8) {
+        if (insn & 0x100) {
+            gen_helper_rol16_cc(dest, cpu_env, reg, shift);
+        } else {
+            gen_helper_ror16_cc(dest, cpu_env, reg, shift);
+        }
+    } else {
+        if (insn & 0x100) {
+            gen_helper_roxl16_cc(dest, cpu_env, reg, shift);
+        } else {
+            gen_helper_roxr16_cc(dest, cpu_env, reg, shift);
+        }
+    }
+    gen_partset_reg(OS_WORD, reg, dest);
+    set_cc_op(s, CC_OP_FLAGS);
+}
+
+DISAS_INSN(rotate_reg)
+{
+    TCGv reg;
+    TCGv src;
+    TCGv tmp;
+
+    reg = DREG(insn, 0);
+    src = DREG(insn, 9);
+    tmp = tcg_temp_new_i32();
+    tcg_gen_andi_i32(tmp, src, 63);
+    if (insn & 8) {
+        if (insn & 0x100) {
+            gen_helper_rol32_cc(reg, cpu_env, reg, tmp);
+        } else {
+            gen_helper_ror32_cc(reg, cpu_env, reg, tmp);
+        }
+    } else {
+        if (insn & 0x100) {
+            gen_helper_roxl32_cc(reg, cpu_env, reg, tmp);
+        } else {
+            gen_helper_roxr32_cc(reg, cpu_env, reg, tmp);
+        }
+    }
+    set_cc_op(s, CC_OP_FLAGS);
+}
+
+DISAS_INSN(rotate8_reg)
+{
+    TCGv reg;
+    TCGv src;
+    TCGv dest;
+    TCGv tmp;
+
+    reg = DREG(insn, 0);
+    src = DREG(insn, 9);
+    tmp = tcg_temp_new_i32();
+    tcg_gen_andi_i32(tmp, src, 63);
+    dest = tcg_temp_new_i32();
+    if (insn & 8) {
+        if (insn & 0x100) {
+            gen_helper_rol8_cc(dest, cpu_env, reg, tmp);
+        } else {
+            gen_helper_ror8_cc(dest, cpu_env, reg, tmp);
+        }
+    } else {
+        if (insn & 0x100) {
+            gen_helper_roxl8_cc(dest, cpu_env, reg, tmp);
+        } else {
+            gen_helper_roxr8_cc(dest, cpu_env, reg, tmp);
+        }
+    }
+    gen_partset_reg(OS_BYTE, reg, dest);
+    set_cc_op(s, CC_OP_FLAGS);
+}
+
+DISAS_INSN(rotate16_reg)
+{
+    TCGv reg;
+    TCGv src;
+    TCGv dest;
+    TCGv tmp;
+
+    reg = DREG(insn, 0);
+    src = DREG(insn, 9);
+    tmp = tcg_temp_new_i32();
+    tcg_gen_andi_i32(tmp, src, 63);
+    dest = tcg_temp_new_i32();
+    if (insn & 8) {
+        if (insn & 0x100) {
+            gen_helper_rol16_cc(dest, cpu_env, reg, tmp);
+        } else {
+            gen_helper_ror16_cc(dest, cpu_env, reg, tmp);
+        }
+    } else {
+        if (insn & 0x100) {
+            gen_helper_roxl16_cc(dest, cpu_env, reg, tmp);
+        } else {
+            gen_helper_roxr16_cc(dest, cpu_env, reg, tmp);
+        }
+    }
+    gen_partset_reg(OS_WORD, reg, dest);
+    set_cc_op(s, CC_OP_FLAGS);
+}
+
+DISAS_INSN(rotate_mem)
+{
+    TCGv src;
+    TCGv dest;
+    TCGv addr;
+    TCGv shift;
+
+    SRC_EA(env, src, OS_WORD, 0, &addr);
+    dest = tcg_temp_new_i32();
+    shift = tcg_const_i32(1);
+    if (insn & 8) {
+        if (insn & 0x100) {
+            gen_helper_rol16_cc(dest, cpu_env, src, shift);
+        } else {
+            gen_helper_ror16_cc(dest, cpu_env, src, shift);
+        }
+    } else {
+        if (insn & 0x100) {
+            gen_helper_roxl16_cc(dest, cpu_env, src, shift);
+        } else {
+            gen_helper_roxr16_cc(dest, cpu_env, src, shift);
+        }
+    }
+    DEST_EA(env, insn, OS_WORD, dest, &addr);
+    set_cc_op(s, CC_OP_FLAGS);
+}
 
 DISAS_INSN(ff1)
 {
@@ -3772,6 +3972,13 @@  void register_m68k_insns (CPUM68KState *env)
     INSN(shift16_reg, e060, f0f0, M68000);
     INSN(shift_reg, e0a0, f0f0, M68000);
     INSN(shift_mem, e0c0, fcc0, M68000);
+    INSN(rotate_im, e090, f0f0, M68000);
+    INSN(rotate8_im, e010, f0f0, M68000);
+    INSN(rotate16_im, e050, f0f0, M68000);
+    INSN(rotate_reg, e0b0, f0f0, M68000);
+    INSN(rotate8_reg, e030, f0f0, M68000);
+    INSN(rotate16_reg, e070, f0f0, M68000);
+    INSN(rotate_mem, e4c0, fcc0, M68000);
     INSN(undef_fpu, f000, f000, CF_ISA_A);
     INSN(fpu,       f200, ffc0, CF_FPU);
     INSN(fbcc,      f280, ffc0, CF_FPU);