From patchwork Sun Aug 9 20:13:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 505450 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id DA8FB1401C7 for ; Mon, 10 Aug 2015 06:14:55 +1000 (AEST) Received: from localhost ([::1]:56105 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZOWzd-0001lF-Uj for incoming@patchwork.ozlabs.org; Sun, 09 Aug 2015 16:14:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52090) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZOWz0-0000UR-8W for qemu-devel@nongnu.org; Sun, 09 Aug 2015 16:14:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZOWyy-0005NX-6H for qemu-devel@nongnu.org; Sun, 09 Aug 2015 16:14:14 -0400 Received: from smtp4-g21.free.fr ([2a01:e0c:1:1599::13]:2631) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZOWyx-0005NK-W2 for qemu-devel@nongnu.org; Sun, 09 Aug 2015 16:14:12 -0400 Received: from Quad.localdomain (unknown [78.238.229.36]) by smtp4-g21.free.fr (Postfix) with ESMTPS id 476BD4C802E; Sun, 9 Aug 2015 22:14:11 +0200 (CEST) From: Laurent Vivier To: qemu-devel@nongnu.org Date: Sun, 9 Aug 2015 22:13:28 +0200 Message-Id: <1439151229-27747-10-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1439151229-27747-1-git-send-email-laurent@vivier.eu> References: <1439151229-27747-1-git-send-email-laurent@vivier.eu> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a01:e0c:1:1599::13 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Andreas Schwab , Laurent Vivier , gerg@uclinux.org Subject: [Qemu-devel] [PATCH for-2.5 09/30] m68k: add X flag helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Laurent Vivier --- target-m68k/helper.c | 12 +++++++++++- target-m68k/helper.h | 4 +++- target-m68k/translate.c | 29 +++++++++++++++++++++-------- 3 files changed, 35 insertions(+), 10 deletions(-) diff --git a/target-m68k/helper.c b/target-m68k/helper.c index c6f5cc0..8c10fbc 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -465,7 +465,17 @@ uint32_t HELPER(addx_cc)(CPUM68KState *env, uint32_t op1, uint32_t op2) return res; } -uint32_t HELPER(xflag_lt)(uint32_t a, uint32_t b) +uint32_t HELPER(xflag_lt_i8)(uint32_t a, uint32_t b) +{ + return (uint8_t)a < (uint8_t)b; +} + +uint32_t HELPER(xflag_lt_i16)(uint32_t a, uint32_t b) +{ + return (uint16_t)a < (uint16_t)b; +} + +uint32_t HELPER(xflag_lt_i32)(uint32_t a, uint32_t b) { return a < b; } diff --git a/target-m68k/helper.h b/target-m68k/helper.h index 81c8e79..81fb7db 100644 --- a/target-m68k/helper.h +++ b/target-m68k/helper.h @@ -8,7 +8,9 @@ DEF_HELPER_3(subx_cc, i32, env, i32, i32) DEF_HELPER_3(shl_cc, i32, env, i32, i32) DEF_HELPER_3(shr_cc, i32, env, i32, i32) DEF_HELPER_3(sar_cc, i32, env, i32, i32) -DEF_HELPER_2(xflag_lt, i32, i32, i32) +DEF_HELPER_2(xflag_lt_i8, i32, i32, i32) +DEF_HELPER_2(xflag_lt_i16, i32, i32, i32) +DEF_HELPER_2(xflag_lt_i32, i32, i32, i32) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 80ac63a..5fa39db 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -488,6 +488,19 @@ static inline void gen_flush_flags(DisasContext *s) } \ } while (0) +#define SET_X_FLAG(opsize, a, b) do { \ + switch (opsize) { \ + case OS_BYTE: \ + gen_helper_xflag_lt_i8(QREG_CC_X, a, b); break; \ + case OS_WORD: \ + gen_helper_xflag_lt_i16(QREG_CC_X, a, b); break; \ + case OS_LONG: \ + gen_helper_xflag_lt_i32(QREG_CC_X, a, b); break; \ + default: \ + abort(); \ + } \ +} while (0) + static void gen_logic_cc(DisasContext *s, TCGv val, int opsize) { tcg_gen_mov_i32(QREG_CC_DEST, val); @@ -1102,10 +1115,10 @@ DISAS_INSN(addsub) } if (add) { tcg_gen_add_i32(dest, tmp, src); - gen_helper_xflag_lt(QREG_CC_X, dest, src); + SET_X_FLAG(OS_LONG, dest, src); set_cc_op(s, CC_OP_ADD); } else { - gen_helper_xflag_lt(QREG_CC_X, tmp, src); + SET_X_FLAG(OS_LONG, tmp, src); tcg_gen_sub_i32(dest, tmp, src); set_cc_op(s, CC_OP_SUB); } @@ -1317,7 +1330,7 @@ DISAS_INSN(arith_im) break; case 2: /* subi */ tcg_gen_mov_i32(dest, src1); - gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); + SET_X_FLAG(OS_LONG, dest, tcg_const_i32(im)); tcg_gen_subi_i32(dest, dest, im); gen_update_cc_add(dest, tcg_const_i32(im)); set_cc_op(s, CC_OP_SUB); @@ -1326,7 +1339,7 @@ DISAS_INSN(arith_im) tcg_gen_mov_i32(dest, src1); tcg_gen_addi_i32(dest, dest, im); gen_update_cc_add(dest, tcg_const_i32(im)); - gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); + SET_X_FLAG(OS_LONG, dest, tcg_const_i32(im)); set_cc_op(s, CC_OP_ADD); break; case 5: /* eori */ @@ -1456,7 +1469,7 @@ DISAS_INSN(neg) tcg_gen_neg_i32(reg, src1); set_cc_op(s, CC_OP_SUB); gen_update_cc_add(reg, src1); - gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1); + SET_X_FLAG(OS_LONG, tcg_const_i32(0), src1); set_cc_op(s, CC_OP_SUB); } @@ -1696,13 +1709,13 @@ DISAS_INSN(addsubq) } else { src2 = tcg_const_i32(val); if (insn & 0x0100) { - gen_helper_xflag_lt(QREG_CC_X, dest, src2); + SET_X_FLAG(OS_LONG, dest, tcg_const_i32(val)); tcg_gen_subi_i32(dest, dest, val); set_cc_op(s, CC_OP_SUB); } else { tcg_gen_addi_i32(dest, dest, val); - gen_helper_xflag_lt(QREG_CC_X, dest, src2); - set_cc_op(s, CC_OP_ADD); + SET_X_FLAG(OS_LONG, dest, tcg_const_i32(val)); + SET_CC_OP(OS_LONG, ADD); } gen_update_cc_add(dest, src2); }