From patchwork Wed Jul 15 11:03:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 495787 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 946D81402BD for ; Wed, 15 Jul 2015 21:05:44 +1000 (AEST) Received: from localhost ([::1]:35183 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFKVS-0004hV-Mb for incoming@patchwork.ozlabs.org; Wed, 15 Jul 2015 07:05:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57842) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFKTJ-0000Pj-5b for qemu-devel@nongnu.org; Wed, 15 Jul 2015 07:03:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZFKTH-0001KF-Pw for qemu-devel@nongnu.org; Wed, 15 Jul 2015 07:03:29 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:47946) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFKTH-0001J8-H8 for qemu-devel@nongnu.org; Wed, 15 Jul 2015 07:03:27 -0400 Received: from weber.rr44.fr ([2001:bc8:30d7:120:7e05:7ff:fe0d:f152]) by hall.aurel32.net with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84) (envelope-from ) id 1ZFKTE-0003Qj-VX; Wed, 15 Jul 2015 13:03:25 +0200 Received: from aurel32 by weber.rr44.fr with local (Exim 4.85) (envelope-from ) id 1ZFKTD-0001hP-CQ; Wed, 15 Jul 2015 13:03:23 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 15 Jul 2015 13:03:15 +0200 Message-Id: <1436958199-5181-6-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436958199-5181-1-git-send-email-aurelien@aurel32.net> References: <1436958199-5181-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:100::1 Cc: Paolo Bonzini , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH RFC 5/9] tcg/i386: implement ext_i32_i64 and extu_i32_i64 ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implementing them as real ops means they can't be optimized out by the register allocator or the optimizer. Cc: Paolo Bonzini Cc: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/i386/tcg-target.c | 5 +++++ tcg/i386/tcg-target.h | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index ff4d9cf..637b1fb 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -2034,9 +2034,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_bswap64_i64: tcg_out_bswap64(s, args[0]); break; + case INDEX_op_extu_i32_i64: case INDEX_op_ext32u_i64: tcg_out_ext32u(s, args[0], args[1]); break; + case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: tcg_out_ext32s(s, args[0], args[1]); break; @@ -2171,6 +2173,9 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_ext16u_i64, { "r", "r" } }, { INDEX_op_ext32u_i64, { "r", "r" } }, + { INDEX_op_ext_i32_i64, { "r", "r" } }, + { INDEX_op_extu_i32_i64, { "r", "r" } }, + { INDEX_op_deposit_i64, { "Q", "0", "Q" } }, { INDEX_op_movcond_i64, { "r", "r", "re", "r", "0" } }, diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 274c97f..16f3949 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -131,8 +131,8 @@ extern bool have_bmi1; /* size changing optional ops */ #define TCG_TARGET_HAS_trunc_shr_i64_i32 0 -#define TCG_TARGET_HAS_ext_i32_i64 0 -#define TCG_TARGET_HAS_extu_i32_i64 0 +#define TCG_TARGET_HAS_ext_i32_i64 1 +#define TCG_TARGET_HAS_extu_i32_i64 1 #endif