From patchwork Thu Jul 9 07:15:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 493280 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5FF281402C4 for ; Thu, 9 Jul 2015 17:18:50 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=rbFP7W/x; dkim-atps=neutral Received: from localhost ([::1]:38139 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZD66Z-0006pv-V6 for incoming@patchwork.ozlabs.org; Thu, 09 Jul 2015 03:18:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39151) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZD64K-0002TV-0S for qemu-devel@nongnu.org; Thu, 09 Jul 2015 03:16:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZD64I-0000PG-N2 for qemu-devel@nongnu.org; Thu, 09 Jul 2015 03:16:27 -0400 Received: from mail-wg0-x232.google.com ([2a00:1450:400c:c00::232]:36187) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZD64I-0000Nr-CN for qemu-devel@nongnu.org; Thu, 09 Jul 2015 03:16:26 -0400 Received: by wgxm20 with SMTP id m20so31759104wgx.3 for ; Thu, 09 Jul 2015 00:16:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=i3/NUEa+Ly7G6ZrtJ0evkPTSiwjNz/AFkW/bWbz5mQs=; b=rbFP7W/xmbgzqVG7Jk7MLcAsH4z/KOm2ava8vgKeJO+w+M8E1vXwL3iRmFsJSLnCQU /TlIfSvqJwUaUOwXGzkyIMUAz5gfn+O9K6mpqjjFb7S5DhHVM1F93ywsgK3SSqPSihRB f04faTd/QAc0Fw5ylL+0arJzd5Uuj2qLCHzygWqPHd13i43XeKgAS+a4GQ2SCfLQB1SI GS9lhYM1p04BjXVLz/AlpEN4ukxbvbFaN3XPrxWqn8HVAZwTR92XvzBSMVtN99+a03sN fIyXTFD8A0ZAeNFrCt0gf1gq6kOgW26ncpwdeF/PlImW0TcIvmMHA3yAX38ESWAzgraf UqrA== X-Received: by 10.180.77.68 with SMTP id q4mr77871794wiw.22.1436426185824; Thu, 09 Jul 2015 00:16:25 -0700 (PDT) Received: from bigtime.twiddle.net (host86-177-156-52.range86-177.btcentralplus.com. [86.177.156.52]) by smtp.gmail.com with ESMTPSA id lq9sm7205575wjb.35.2015.07.09.00.16.20 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Jul 2015 00:16:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 Jul 2015 08:15:16 +0100 Message-Id: <1436426122-12276-5-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1436426122-12276-1-git-send-email-rth@twiddle.net> References: <1436426122-12276-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:400c:c00::232 Cc: Paolo Bonzini Subject: [Qemu-devel] [PATCH 04/10] target-i386: Use gen_lea_v_seg in stack subroutines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org I.e. gen_push_v, gen_pop_T0, gen_stack_A0. More centralization of handling of segment bases. Signed-off-by: Richard Henderson --- target-i386/translate.c | 52 +++++++++++++------------------------------------ 1 file changed, 13 insertions(+), 39 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index d85e800..89eeeef 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -465,10 +465,9 @@ static inline void gen_jmp_im(target_ulong pc) /* Compute SEG:REG into A0. SEG is selected from the override segment (OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to indicate no override. */ -static void gen_lea_v_seg(DisasContext *s, TCGv a0, int def_seg, int ovr_seg) +static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0, + int def_seg, int ovr_seg) { - TCGMemOp aflag = s->aflag; - switch (aflag) { #ifdef TARGET_X86_64 case MO_64: @@ -526,12 +525,12 @@ static void gen_lea_v_seg(DisasContext *s, TCGv a0, int def_seg, int ovr_seg) static inline void gen_string_movl_A0_ESI(DisasContext *s) { - gen_lea_v_seg(s, cpu_regs[R_ESI], R_DS, s->override); + gen_lea_v_seg(s, s->aflag, cpu_regs[R_ESI], R_DS, s->override); } static inline void gen_string_movl_A0_EDI(DisasContext *s) { - gen_lea_v_seg(s, cpu_regs[R_EDI], R_ES, -1); + gen_lea_v_seg(s, s->aflag, cpu_regs[R_EDI], R_ES, -1); } static inline void gen_op_movl_T0_Dshift(TCGMemOp ot) @@ -1983,7 +1982,7 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm) tcg_abort(); } - gen_lea_v_seg(s, sum, def_seg, ovr_seg); + gen_lea_v_seg(s, s->aflag, sum, def_seg, ovr_seg); } static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm) @@ -2046,7 +2045,7 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm) /* used for LEA and MOV AX, mem */ static void gen_add_A0_ds_seg(DisasContext *s) { - gen_lea_v_seg(s, cpu_A0, R_DS, s->override); + gen_lea_v_seg(s, s->aflag, cpu_A0, R_DS, s->override); } /* generate modrm memory load or store of 'reg'. TMP0 is used if reg == @@ -2274,21 +2273,12 @@ static void gen_push_v(DisasContext *s, TCGv val) tcg_gen_subi_tl(cpu_A0, cpu_regs[R_ESP], size); - if (CODE64(s)) { - /* No special handling. */ - } else if (s->ss32) { + if (!CODE64(s)) { if (s->addseg) { new_esp = cpu_tmp4; tcg_gen_mov_tl(new_esp, cpu_A0); - gen_op_addl_A0_seg(s, R_SS); - } else { - tcg_gen_ext32u_tl(cpu_A0, cpu_A0); } - } else { - new_esp = cpu_tmp4; - tcg_gen_ext16u_tl(cpu_A0, cpu_A0); - tcg_gen_mov_tl(new_esp, cpu_A0); - gen_op_addl_A0_seg(s, R_SS); + gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1); } gen_op_st_v(s, d_ot, val, cpu_A0); @@ -2299,37 +2289,21 @@ static void gen_push_v(DisasContext *s, TCGv val) static TCGMemOp gen_pop_T0(DisasContext *s) { TCGMemOp d_ot = mo_pushpop(s, s->dflag); - TCGv addr = cpu_A0; - if (CODE64(s)) { - addr = cpu_regs[R_ESP]; - } else if (!s->ss32) { - tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESP]); - gen_op_addl_A0_seg(s, R_SS); - } else if (s->addseg) { - tcg_gen_mov_tl(cpu_A0, cpu_regs[R_ESP]); - gen_op_addl_A0_seg(s, R_SS); - } else { - tcg_gen_ext32u_tl(cpu_A0, cpu_regs[R_ESP]); - } + gen_lea_v_seg(s, mo_stacksize(s), cpu_regs[R_ESP], R_SS, -1); + gen_op_ld_v(s, d_ot, cpu_T[0], cpu_A0); - gen_op_ld_v(s, d_ot, cpu_T[0], addr); return d_ot; } -static void gen_pop_update(DisasContext *s, TCGMemOp ot) +static inline void gen_pop_update(DisasContext *s, TCGMemOp ot) { gen_stack_update(s, 1 << ot); } -static void gen_stack_A0(DisasContext *s) +static inline void gen_stack_A0(DisasContext *s) { - gen_op_movl_A0_reg(R_ESP); - if (!s->ss32) - tcg_gen_ext16u_tl(cpu_A0, cpu_A0); - tcg_gen_mov_tl(cpu_T[1], cpu_A0); - if (s->addseg) - gen_op_addl_A0_seg(s, R_SS); + gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_16, cpu_regs[R_ESP], R_SS, -1); } /* NOTE: wrap around in 16 bit not fully handled */