From patchwork Tue Jul 7 17:16:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 492416 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 754D21401F6 for ; Wed, 8 Jul 2015 03:17:26 +1000 (AEST) Received: from localhost ([::1]:59610 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZCWUm-00020f-Ih for incoming@patchwork.ozlabs.org; Tue, 07 Jul 2015 13:17:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57068) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZCWU5-0000jw-5n for qemu-devel@nongnu.org; Tue, 07 Jul 2015 13:16:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZCWU0-00068o-7v for qemu-devel@nongnu.org; Tue, 07 Jul 2015 13:16:41 -0400 Received: from cantor2.suse.de ([195.135.220.15]:49789 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZCWU0-00067j-1R for qemu-devel@nongnu.org; Tue, 07 Jul 2015 13:16:36 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 8273CABA5; Tue, 7 Jul 2015 17:16:35 +0000 (UTC) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Tue, 7 Jul 2015 19:16:29 +0200 Message-Id: <1436289389-5403-23-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436289389-5403-1-git-send-email-afaerber@suse.de> References: <1436289389-5403-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 195.135.220.15 Cc: "Edgar E. Iglesias" , Peter Crosthwaite , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Peter Crosthwaite Subject: [Qemu-devel] [PULL v2 22/22] disas: cris: QOMify target specific disas setup X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite Move the target_disas() cris specifics to the QOM disas_set_info() hook and delete the cris specific code in disas.c. This also now adds support for monitor_disas() to cris. E.g. (qemu) xp 0x40004000 0000000040004000: 0x1e6f25f0 And before this patch: (qemu) xp/i 0x40004000 0x40004000: Asm output not supported on this arch After: (qemu) xp/i 0x40004000 0x40004000: di (qemu) xp/i 0x40004002 0x40004002: move.d 0xb003c004,$r1 Note: second example is 6-byte misaligned instruction! Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Crosthwaite Signed-off-by: Andreas Färber --- disas.c | 8 -------- target-cris/cpu.c | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/disas.c b/disas.c index 937e08b..69a6066 100644 --- a/disas.c +++ b/disas.c @@ -257,14 +257,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code, #elif defined(TARGET_ALPHA) s.info.mach = bfd_mach_alpha_ev6; s.info.print_insn = print_insn_alpha; -#elif defined(TARGET_CRIS) - if (flags != 32) { - s.info.mach = bfd_mach_cris_v0_v10; - s.info.print_insn = print_insn_crisv10; - } else { - s.info.mach = bfd_mach_cris_v32; - s.info.print_insn = print_insn_crisv32; - } #elif defined(TARGET_S390X) s.info.mach = bfd_mach_s390_64; s.info.print_insn = print_insn_s390; diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 0db209b..b17e849 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -161,6 +161,20 @@ static void cris_cpu_set_irq(void *opaque, int irq, int level) } #endif +static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) +{ + CRISCPU *cc = CRIS_CPU(cpu); + CPUCRISState *env = &cc->env; + + if (env->pregs[PR_VR] != 32) { + info->mach = bfd_mach_cris_v0_v10; + info->print_insn = print_insn_crisv10; + } else { + info->mach = bfd_mach_cris_v32; + info->print_insn = print_insn_crisv32; + } +} + static void cris_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); @@ -292,6 +306,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_num_core_regs = 49; cc->gdb_stop_before_watchpoint = true; + + cc->disas_set_info = cris_disas_set_info; } static const TypeInfo cris_cpu_type_info = {