From patchwork Fri Jun 26 05:27:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Ungerer X-Patchwork-Id: 488608 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 62B29140271 for ; Fri, 26 Jun 2015 15:28:35 +1000 (AEST) Received: from localhost ([::1]:58343 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z8MBl-000610-B8 for incoming@patchwork.ozlabs.org; Fri, 26 Jun 2015 01:28:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59883) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z8M9g-0002Er-N0 for qemu-devel@nongnu.org; Fri, 26 Jun 2015 01:26:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z8M9b-0004rG-Ob for qemu-devel@nongnu.org; Fri, 26 Jun 2015 01:26:24 -0400 Received: from nschwmtas04p.mx.bigpond.com ([61.9.189.146]:36087) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z8M9b-0004pi-1O for qemu-devel@nongnu.org; Fri, 26 Jun 2015 01:26:19 -0400 Received: from nschwcmgw07p ([61.9.190.167]) by nschwmtas04p.mx.bigpond.com with ESMTP id <20150626052615.QDYJ15081.nschwmtas04p.mx.bigpond.com@nschwcmgw07p>; Fri, 26 Jun 2015 05:26:15 +0000 Received: from goober.accelecon.com ([149.135.16.88]) by nschwcmgw07p with BigPond Outbound id ktSD1q00P1u0AeD01tSF8N; Fri, 26 Jun 2015 05:26:15 +0000 X-Authority-Analysis: v=2.0 cv=Os7NOlDt c=1 sm=1 a=tpHzvNDyw14p4wpd1xf5Bw==:17 a=abLpnCq0AAAA:8 a=pGLkceISAAAA:8 a=uP1ucDPQAAAA:8 a=0ijfLpvSn4Ui0UTgeZMA:9 a=xOBCqR2dTQaDpeUD:21 a=GBXWMPinOzHCgV7f:21 a=tpHzvNDyw14p4wpd1xf5Bw==:117 From: gerg@uclinux.org To: qemu-devel@nongnu.org Date: Fri, 26 Jun 2015 15:27:13 +1000 Message-Id: <1435296436-12152-2-git-send-email-gerg@uclinux.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1435296436-12152-1-git-send-email-gerg@uclinux.org> References: <1435296436-12152-1-git-send-email-gerg@uclinux.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 61.9.189.146 Cc: Greg Ungerer Subject: [Qemu-devel] [PATCH 1/4] hw/net: create common collection of MII definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Greg Ungerer Create a common set of definitions of address and register values for ethernet MII phys. A few of the current ethernet drivers have at least a partial set of these definitions. Others just use hard coded raw constant numbers. This initial set is copied directly from the allwinner_emac code. Signed-off-by: Greg Ungerer --- include/hw/net/allwinner_emac.h | 40 +------------------------- include/hw/net/mii.h | 64 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 39 deletions(-) create mode 100644 include/hw/net/mii.h diff --git a/include/hw/net/allwinner_emac.h b/include/hw/net/allwinner_emac.h index 5ae7717..9f21aa7 100644 --- a/include/hw/net/allwinner_emac.h +++ b/include/hw/net/allwinner_emac.h @@ -24,6 +24,7 @@ #include "net/net.h" #include "qemu/fifo8.h" +#include "hw/net/mii.h" #define TYPE_AW_EMAC "allwinner-emac" #define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC) @@ -118,45 +119,6 @@ #define EMAC_RX_IO_DATA_STATUS_OK (1 << 7) #define EMAC_UNDOCUMENTED_MAGIC 0x0143414d /* header for RX frames */ -/* PHY registers */ -#define MII_BMCR 0 -#define MII_BMSR 1 -#define MII_PHYID1 2 -#define MII_PHYID2 3 -#define MII_ANAR 4 -#define MII_ANLPAR 5 -#define MII_ANER 6 -#define MII_NSR 16 -#define MII_LBREMR 17 -#define MII_REC 18 -#define MII_SNRDR 19 -#define MII_TEST 25 - -/* PHY registers fields */ -#define MII_BMCR_RESET (1 << 15) -#define MII_BMCR_LOOPBACK (1 << 14) -#define MII_BMCR_SPEED (1 << 13) -#define MII_BMCR_AUTOEN (1 << 12) -#define MII_BMCR_FD (1 << 8) - -#define MII_BMSR_100TX_FD (1 << 14) -#define MII_BMSR_100TX_HD (1 << 13) -#define MII_BMSR_10T_FD (1 << 12) -#define MII_BMSR_10T_HD (1 << 11) -#define MII_BMSR_MFPS (1 << 6) -#define MII_BMSR_AN_COMP (1 << 5) -#define MII_BMSR_AUTONEG (1 << 3) -#define MII_BMSR_LINK_ST (1 << 2) - -#define MII_ANAR_TXFD (1 << 8) -#define MII_ANAR_TX (1 << 7) -#define MII_ANAR_10FD (1 << 6) -#define MII_ANAR_10 (1 << 5) -#define MII_ANAR_CSMACD (1 << 0) - -#define RTL8201CP_PHYID1 0x0000 -#define RTL8201CP_PHYID2 0x8201 - /* INT CTL and INT STA registers fields */ #define EMAC_INT_TX_CHAN(x) (1 << (x)) #define EMAC_INT_RX (1 << 8) diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h new file mode 100644 index 0000000..4d93114 --- /dev/null +++ b/include/hw/net/mii.h @@ -0,0 +1,64 @@ +/* + * Common network MII address and register definitions. + * + * Copyright (C) 2014 Beniamino Galvani + * + * Allwinner EMAC register definitions from Linux kernel are: + * Copyright 2012 Stefan Roese + * Copyright 2013 Maxime Ripard + * Copyright 1997 Sten Wang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef MII_H +#define MII_H + +/* PHY registers */ +#define MII_BMCR 0 +#define MII_BMSR 1 +#define MII_PHYID1 2 +#define MII_PHYID2 3 +#define MII_ANAR 4 +#define MII_ANLPAR 5 +#define MII_ANER 6 +#define MII_NSR 16 +#define MII_LBREMR 17 +#define MII_REC 18 +#define MII_SNRDR 19 +#define MII_TEST 25 + +/* PHY registers fields */ +#define MII_BMCR_RESET (1 << 15) +#define MII_BMCR_LOOPBACK (1 << 14) +#define MII_BMCR_SPEED (1 << 13) +#define MII_BMCR_AUTOEN (1 << 12) +#define MII_BMCR_FD (1 << 8) + +#define MII_BMSR_100TX_FD (1 << 14) +#define MII_BMSR_100TX_HD (1 << 13) +#define MII_BMSR_10T_FD (1 << 12) +#define MII_BMSR_10T_HD (1 << 11) +#define MII_BMSR_MFPS (1 << 6) +#define MII_BMSR_AN_COMP (1 << 5) +#define MII_BMSR_AUTONEG (1 << 3) +#define MII_BMSR_LINK_ST (1 << 2) + +#define MII_ANAR_TXFD (1 << 8) +#define MII_ANAR_TX (1 << 7) +#define MII_ANAR_10FD (1 << 6) +#define MII_ANAR_10 (1 << 5) +#define MII_ANAR_CSMACD (1 << 0) + +/* List of vendor identifiers */ +#define RTL8201CP_PHYID1 0x0000 +#define RTL8201CP_PHYID2 0x8201 + +#endif /* MII_H */