From patchwork Fri Jun 19 13:43:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Ungerer X-Patchwork-Id: 486709 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8A7A3140129 for ; Fri, 19 Jun 2015 23:43:58 +1000 (AEST) Received: from localhost ([::1]:58125 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5waK-0002aT-NY for incoming@patchwork.ozlabs.org; Fri, 19 Jun 2015 09:43:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34274) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5wZl-0001VG-0r for qemu-devel@nongnu.org; Fri, 19 Jun 2015 09:43:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z5wZg-00076R-7i for qemu-devel@nongnu.org; Fri, 19 Jun 2015 09:43:20 -0400 Received: from nskntmtas01p.mx.bigpond.com ([61.9.168.137]:16601) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5wZf-00075t-RG for qemu-devel@nongnu.org; Fri, 19 Jun 2015 09:43:16 -0400 Received: from nskntcmgw06p ([61.9.169.166]) by nskntmtas01p.mx.bigpond.com with ESMTP id <20150619134313.ZZOZ14443.nskntmtas01p.mx.bigpond.com@nskntcmgw06p>; Fri, 19 Jun 2015 13:43:13 +0000 Received: from goober.accelecon.com ([149.135.16.88]) by nskntcmgw06p with BigPond Outbound id iDiW1q00l1u0AeD01Dj80D; Fri, 19 Jun 2015 13:43:13 +0000 X-Authority-Analysis: v=2.0 cv=RsdH3VaK c=1 sm=1 a=tpHzvNDyw14p4wpd1xf5Bw==:17 a=abLpnCq0AAAA:8 a=Am4ss40yAAAA:8 a=LNb0EpMPLjd40HMBQnEA:9 a=tpHzvNDyw14p4wpd1xf5Bw==:117 From: gerg@uclinux.org To: qemu-devel@nongnu.org Date: Fri, 19 Jun 2015 23:43:26 +1000 Message-Id: <1434721406-25288-4-git-send-email-gerg@uclinux.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1434721406-25288-1-git-send-email-gerg@uclinux.org> References: <1434721406-25288-1-git-send-email-gerg@uclinux.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 61.9.168.137 Cc: peter.maydell@linaro.org, Greg Ungerer Subject: [Qemu-devel] [PATCH v2 3/3] m68k: fix usp processing on interrupt entry and exception exit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Greg Ungerer The action to potentially switch sp register is not occurring at the correct point in the interrupt entry or exception exit sequences. For the interrupt entry case the sp on entry is used to create the stack exception frame - but this may well be the user stack pointer, since we haven't done the switch yet. Re-order the flow to switch the sp regs then use the current sp to create the exception frame. For the return from exception case the code is unwinding the sp after switching sp registers. But it should always unwind the supervisor sp first, then carry out any required sp switch. Note that these problems don't effect operation unless the user sp bit is set in the CACR register. Only a single sp is used in the default power up state. Previously Linux only used this single sp mode. But modern versions of Linux use the user sp mode now, so we need correct behavior for Linux to work. Signed-off-by: Greg Ungerer Reviewed-by: Peter Crosthwaite Reviewed-by: Laurent Vivier --- target-m68k/op_helper.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index 06661f5..3a0d16f 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -63,8 +63,8 @@ static void do_rte(CPUM68KState *env) env->pc = cpu_ldl_kernel(env, sp + 4); sp |= (fmt >> 28) & 3; env->sr = fmt & 0xffff; - m68k_switch_sp(env); env->aregs[7] = sp + 8; + m68k_switch_sp(env); } static void do_interrupt_all(CPUM68KState *env, int is_hw) @@ -108,10 +108,7 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw) vector = cs->exception_index << 2; - sp = env->aregs[7]; - fmt |= 0x40000000; - fmt |= (sp & 3) << 28; fmt |= vector << 16; fmt |= env->sr; @@ -121,6 +118,8 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw) env->sr &= ~SR_M; } m68k_switch_sp(env); + sp = env->aregs[7]; + fmt |= (sp & 3) << 28; /* ??? This could cause MMU faults. */ sp &= ~3;