From patchwork Mon Jun 15 20:31:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Aurelio C. Remonda" X-Patchwork-Id: 484529 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 62D101401F6 for ; Tue, 16 Jun 2015 06:31:35 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=mcLk3eI+; dkim-atps=neutral Received: from localhost ([::1]:36336 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4b2a-0001FR-Jh for incoming@patchwork.ozlabs.org; Mon, 15 Jun 2015 16:31:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48648) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4b2L-0000yt-R4 for qemu-devel@nongnu.org; Mon, 15 Jun 2015 16:31:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z4b2G-00061P-Gq for qemu-devel@nongnu.org; Mon, 15 Jun 2015 16:31:17 -0400 Received: from mail-qk0-x236.google.com ([2607:f8b0:400d:c09::236]:36741) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4b2G-00061B-9s for qemu-devel@nongnu.org; Mon, 15 Jun 2015 16:31:12 -0400 Received: by qkfe185 with SMTP id e185so19725733qkf.3 for ; Mon, 15 Jun 2015 13:31:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id; bh=7av6BfpXSBFlv4AqWcSTnhCrDkJLI5lJiU5GJg1rhhE=; b=mcLk3eI+qnsdtgUhA6ydzrPVG66W4vUPRtt+2DpURi0TCwvurNc0vtfwnTLXhnAfTF DE3reglrbUkvYJyqkEYyIcH/UrPAqOXpx0Ajo20306/H5NYb62+YgDjbGyvGndt8Cboc TCXhwIgfiARJGvDUyfkMTetEqRwrScZATxAXEbcm5A00O9VnfP7KtQu3OfNIt+6USprz iI77miP7zu7ulTb/WwyuN1ZlW2zRzUctFWL1jH2i/O6oMh09lPLFEES1K9/XVlCEutwb CyPafQr0gcv/+9NXBKQU5M00MY5why7A8n8HUX7WIuq5cPQ3+yim57jwy+ccF2nvuBfr PsZA== X-Received: by 10.140.235.147 with SMTP id g141mr38893194qhc.35.1434400271461; Mon, 15 Jun 2015 13:31:11 -0700 (PDT) Received: from localhost.localdomain ([181.31.133.97]) by mx.google.com with ESMTPSA id e104sm6901053qgd.29.2015.06.15.13.31.08 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 15 Jun 2015 13:31:10 -0700 (PDT) From: "Aurelio C. Remonda" To: qemu-devel@nongnu.org, ilg@livius.net, peter.maydell@linaro.org, martin.galvan@tallertechnologies.com, daniel.gutson@tallertechnologies.com Date: Mon, 15 Jun 2015 17:31:00 -0300 Message-Id: <1434400260-5191-1-git-send-email-aurelioremonda@gmail.com> X-Mailer: git-send-email 1.9.1 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c09::236 Subject: [Qemu-devel] [PATCH V3] Target-arm: Add the Cortex-M4 CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds the Cortex-M4 CPU. The M4 is basically the same as the M3, the main differences being the DSP instructions and an optional FPU. Created an ARM_FEATURE_THUMB_DSP to be added to any non-M thumb2-compatible CPU that uses DSP instructions, and manually added it to the M4 in its initfn. Signed-off-by: Aurelio C. Remonda --- * Changes in V3: Add the ARM_FEATURE_THUMB_DSP in a separate patch and create just the CPU init on this one. target-arm/cpu.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 4a888ab..4950897 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -783,6 +783,21 @@ static void cortex_m3_initfn(Object *obj) cpu->midr = 0x410fc231; } +static void cortex_m4_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr = 0x410fc240; + /*main id register CPUID bit assignments + Bits NAME Function + [31:24] IMPLEMENTER Indicates implementor: 0x41 = ARM + [23:20] VARIANT Indicates processor revision: 0x0 = Revision 0 + [19:16] (Constant) Reads as 0xF + [15:4] PARTNO Indicates part number: 0xC24 = Cortex-M4 + [3:0] REVISION Indicates patch release: 0x0 = Patch 0.*/ +} static void arm_v7m_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); @@ -1185,6 +1200,8 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, { .name = "cortex-m3", .initfn = cortex_m3_initfn, .class_init = arm_v7m_class_init }, + { .name = "cortex-m4", .initfn = cortex_m4_initfn, + .class_init = arm_v7m_class_init }, { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, { .name = "cortex-a15", .initfn = cortex_a15_initfn },