From patchwork Mon Jun 15 18:49:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 484506 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 099B0140325 for ; Tue, 16 Jun 2015 04:50:12 +1000 (AEST) Received: from localhost ([::1]:36033 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4ZSU-0000YM-8X for incoming@patchwork.ozlabs.org; Mon, 15 Jun 2015 14:50:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42078) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4ZSE-00009a-K1 for qemu-devel@nongnu.org; Mon, 15 Jun 2015 14:49:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z4ZSC-0003my-5v for qemu-devel@nongnu.org; Mon, 15 Jun 2015 14:49:54 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34473) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4ZSB-0003mr-Vf for qemu-devel@nongnu.org; Mon, 15 Jun 2015 14:49:52 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Z4ZSA-0003bl-Cd; Mon, 15 Jun 2015 19:49:50 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 15 Jun 2015 19:49:50 +0100 Message-Id: <1434394190-13837-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1434394190-13837-1-git-send-email-peter.maydell@linaro.org> References: <1434394190-13837-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: =?UTF-8?q?Alex=20Z=C3=BCpke?= , patches@linaro.org Subject: [Qemu-devel] [PATCH 2/2] target-arm: Implement YIELD insn to yield in ARM and Thumb translators X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implement the YIELD instruction in the ARM and Thumb translators to actually yield control back to the top level loop rather than being a simple no-op. (We already do this for A64.) Signed-off-by: Peter Maydell --- target-arm/translate.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target-arm/translate.c b/target-arm/translate.c index ead08f4..05da26b 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4080,6 +4080,10 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr) static void gen_nop_hint(DisasContext *s, int val) { switch (val) { + case 1: /* yield */ + gen_set_pc_im(s, s->pc); + s->is_jmp = DISAS_YIELD; + break; case 3: /* wfi */ gen_set_pc_im(s, s->pc); s->is_jmp = DISAS_WFI; @@ -11459,6 +11463,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, case DISAS_WFE: gen_helper_wfe(cpu_env); break; + case DISAS_YIELD: + gen_helper_yield(cpu_env); + break; case DISAS_SWI: gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), default_exception_el(dc));