From patchwork Mon Jun 15 17:24:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 484464 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 221AB140281 for ; Tue, 16 Jun 2015 03:33:04 +1000 (AEST) Received: from localhost ([::1]:35668 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4YFq-0004uj-8I for incoming@patchwork.ozlabs.org; Mon, 15 Jun 2015 13:33:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60859) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Y8H-0007fR-19 for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z4Y8E-0001Ti-F3 for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:12 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34471) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Y8E-0001AA-5K for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:10 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Z4Y83-0003WY-78 for qemu-devel@nongnu.org; Mon, 15 Jun 2015 18:24:59 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 15 Jun 2015 18:24:46 +0100 Message-Id: <1434389098-13430-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1434389098-13430-1-git-send-email-peter.maydell@linaro.org> References: <1434389098-13430-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 16/28] hw/sd/pxa2xx_mmci: Stop using old_mmio in MemoryRegionOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Update the pxa2xx_mmci device to stop using the old_mmio read and write callbacks in its MemoryRegionOps. This actually simplifies the code because the separate byte/halfword/word access functions were all calling into a single function to do the work anyway. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite Message-id: 1434117989-7367-6-git-send-email-peter.maydell@linaro.org --- hw/sd/pxa2xx_mmci.c | 68 +++++++---------------------------------------------- 1 file changed, 8 insertions(+), 60 deletions(-) diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c index ac3ab39..d1fe6d5 100644 --- a/hw/sd/pxa2xx_mmci.c +++ b/hw/sd/pxa2xx_mmci.c @@ -48,7 +48,6 @@ struct PXA2xxMMCIState { int resp_len; int cmdreq; - int ac_width; }; #define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */ @@ -215,7 +214,7 @@ static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s) pxa2xx_mmci_fifo_update(s); } -static uint32_t pxa2xx_mmci_read(void *opaque, hwaddr offset) +static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size) { PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; uint32_t ret; @@ -257,8 +256,8 @@ static uint32_t pxa2xx_mmci_read(void *opaque, hwaddr offset) return 0; case MMC_RXFIFO: ret = 0; - while (s->ac_width -- && s->rx_len) { - ret |= s->rx_fifo[s->rx_start ++] << (s->ac_width << 3); + while (size-- && s->rx_len) { + ret |= s->rx_fifo[s->rx_start++] << (size << 3); s->rx_start &= 0x1f; s->rx_len --; } @@ -277,7 +276,7 @@ static uint32_t pxa2xx_mmci_read(void *opaque, hwaddr offset) } static void pxa2xx_mmci_write(void *opaque, - hwaddr offset, uint32_t value) + hwaddr offset, uint64_t value, unsigned size) { PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; @@ -370,9 +369,9 @@ static void pxa2xx_mmci_write(void *opaque, break; case MMC_TXFIFO: - while (s->ac_width -- && s->tx_len < 0x20) + while (size-- && s->tx_len < 0x20) s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] = - (value >> (s->ac_width << 3)) & 0xff; + (value >> (size << 3)) & 0xff; s->intreq &= ~INT_TXFIFO_REQ; pxa2xx_mmci_fifo_update(s); break; @@ -386,60 +385,9 @@ static void pxa2xx_mmci_write(void *opaque, } } -static uint32_t pxa2xx_mmci_readb(void *opaque, hwaddr offset) -{ - PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; - s->ac_width = 1; - return pxa2xx_mmci_read(opaque, offset); -} - -static uint32_t pxa2xx_mmci_readh(void *opaque, hwaddr offset) -{ - PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; - s->ac_width = 2; - return pxa2xx_mmci_read(opaque, offset); -} - -static uint32_t pxa2xx_mmci_readw(void *opaque, hwaddr offset) -{ - PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; - s->ac_width = 4; - return pxa2xx_mmci_read(opaque, offset); -} - -static void pxa2xx_mmci_writeb(void *opaque, - hwaddr offset, uint32_t value) -{ - PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; - s->ac_width = 1; - pxa2xx_mmci_write(opaque, offset, value); -} - -static void pxa2xx_mmci_writeh(void *opaque, - hwaddr offset, uint32_t value) -{ - PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; - s->ac_width = 2; - pxa2xx_mmci_write(opaque, offset, value); -} - -static void pxa2xx_mmci_writew(void *opaque, - hwaddr offset, uint32_t value) -{ - PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; - s->ac_width = 4; - pxa2xx_mmci_write(opaque, offset, value); -} - static const MemoryRegionOps pxa2xx_mmci_ops = { - .old_mmio = { - .read = { pxa2xx_mmci_readb, - pxa2xx_mmci_readh, - pxa2xx_mmci_readw, }, - .write = { pxa2xx_mmci_writeb, - pxa2xx_mmci_writeh, - pxa2xx_mmci_writew, }, - }, + .read = pxa2xx_mmci_read, + .write = pxa2xx_mmci_write, .endianness = DEVICE_NATIVE_ENDIAN, };