[09/13] target-mips: microMIPS32 R6 POOL32F instructions

Message ID	1434117743-53520-10-git-send-email-yongbok.kim@imgtec.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Yongbok Kim <yongbok.kim@imgtec.com> To: <qemu-devel@nongnu.org> Date: Fri, 12 Jun 2015 15:02:19 +0100 Message-ID: <1434117743-53520-10-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1434117743-53520-1-git-send-email-yongbok.kim@imgtec.com> References: <1434117743-53520-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Cc: leon.alrae@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 09/13] target-mips: microMIPS32 R6 POOL32F instructions Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org

diff --git a/target-mips/translate.c b/target-mips/translate.c index 9422de0..3d9145c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -13963,6 +13963,14 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, goto pool32f_invalid; } break; + case CMP_CONDN_S: + check_insn(ctx, ISA_MIPS32R6); + gen_r6_cmp_s(ctx, ctx->opcode >> 6 & 0x1f, rt, rs, rd); + break; + case CMP_CONDN_D: + check_insn(ctx, ISA_MIPS32R6); + gen_r6_cmp_d(ctx, ctx->opcode >> 6 & 0x1f, rt, rs, rd); + break; case POOL32FXF: gen_pool32fxf(ctx, rt, rs); break; @@ -13991,6 +13999,19 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, goto pool32f_invalid; } break; + case MIN_FMT: + check_insn(ctx, ISA_MIPS32R6); + switch (ctx->opcode >> 9 & 0x3) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0); + break; + default: + goto pool32f_invalid; + } + break; case 0x08: /* [LS][WDU]XC1 */ switch ((ctx->opcode >> 6) & 0x7) { @@ -14024,6 +14045,19 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, goto pool32f_invalid; } break; + case MAX_FMT: + check_insn(ctx, ISA_MIPS32R6); + switch (ctx->opcode >> 9 & 0x3) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0); + break; + default: + goto pool32f_invalid; + } + break; case 0x18: /* 3D insns */ check_insn_opc_removed(ctx, ISA_MIPS32R6); @@ -14072,38 +14106,66 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, } break; case 0x20: - /* MOV[FT].fmt and PREFX */ + /* MOV[FT].fmt, PREFX, RINT.fmt, CLASS.fmt*/ cc = (ctx->opcode >> 13) & 0x7; fmt = (ctx->opcode >> 9) & 0x3; switch ((ctx->opcode >> 6) & 0x7) { case MOVF_FMT: - switch (fmt) { - case FMT_SDPS_S: - gen_movcf_s(ctx, rs, rt, cc, 0); - break; - case FMT_SDPS_D: - gen_movcf_d(ctx, rs, rt, cc, 0); - break; - case FMT_SDPS_PS: - gen_movcf_ps(ctx, rs, rt, cc, 0); - break; - default: - goto pool32f_invalid; + /* RINT_FMT */ + if (ctx->insn_flags & ISA_MIPS32R6) { + switch (fmt) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0); + break; + default: + goto pool32f_invalid; + } + } else { + switch (fmt) { + case FMT_SDPS_S: + gen_movcf_s(ctx, rs, rt, cc, 0); + break; + case FMT_SDPS_D: + gen_movcf_d(ctx, rs, rt, cc, 0); + break; + case FMT_SDPS_PS: + gen_movcf_ps(ctx, rs, rt, cc, 0); + break; + default: + goto pool32f_invalid; + } } break; case MOVT_FMT: - switch (fmt) { - case FMT_SDPS_S: - gen_movcf_s(ctx, rs, rt, cc, 1); - break; - case FMT_SDPS_D: - gen_movcf_d(ctx, rs, rt, cc, 1); - break; - case FMT_SDPS_PS: - gen_movcf_ps(ctx, rs, rt, cc, 1); - break; - default: - goto pool32f_invalid; + /* CLASS_FMT */ + if (ctx->insn_flags & ISA_MIPS32R6) { + switch (fmt) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0); + break; + default: + goto pool32f_invalid; + } + } else { + switch (fmt) { + case FMT_SDPS_S: + gen_movcf_s(ctx, rs, rt, cc, 1); + break; + case FMT_SDPS_D: + gen_movcf_d(ctx, rs, rt, cc, 1); + break; + case FMT_SDPS_PS: + gen_movcf_ps(ctx, rs, rt, cc, 1); + break; + default: + goto pool32f_invalid; + } } break; case PREFX: @@ -14127,6 +14189,32 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, default: \ goto pool32f_invalid; \ } + case MINA_FMT: + check_insn(ctx, ISA_MIPS32R6); + switch (ctx->opcode >> 9 & 0x3) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0); + break; + default: + goto pool32f_invalid; + } + break; + case MAXA_FMT: + check_insn(ctx, ISA_MIPS32R6); + switch (ctx->opcode >> 9 & 0x3) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0); + break; + default: + goto pool32f_invalid; + } + break; case 0x30: /* regular FP ops */ switch ((ctx->opcode >> 6) & 0x3) { @@ -14155,13 +14243,88 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, break; case 0x38: /* cmovs */ - switch ((ctx->opcode >> 6) & 0x3) { + switch ((ctx->opcode >> 6) & 0x7) { case MOVN_FMT: + /* SELNEZ_FMT */ + if (ctx->insn_flags & ISA_MIPS32R6) { + switch (ctx->opcode >> 9 & 0x3) { + case FMT_SDPS_S: + gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs); + break; + case FMT_SDPS_D: + gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs); + break; + default: + goto pool32f_invalid; + } + } else { + FINSN_3ARG_SDPS(MOVN); + } + break; + case MOVN_FMT_04: + check_insn_opc_removed(ctx, ISA_MIPS32R6); FINSN_3ARG_SDPS(MOVN); break; case MOVZ_FMT: + /* SELEQZ_FMT */ + if (ctx->insn_flags & ISA_MIPS32R6) { + switch (ctx->opcode >> 9 & 0x3) { + case FMT_SDPS_S: + gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs); + break; + case FMT_SDPS_D: + gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs); + break; + default: + goto pool32f_invalid; + } + } else { + FINSN_3ARG_SDPS(MOVZ); + } + break; + case MOVZ_FMT_05: + check_insn_opc_removed(ctx, ISA_MIPS32R6); FINSN_3ARG_SDPS(MOVZ); break; + case SEL_FMT: + check_insn(ctx, ISA_MIPS32R6); + switch (ctx->opcode >> 9 & 0x3) { + case FMT_SDPS_S: + gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs); + break; + case FMT_SDPS_D: + gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs); + break; + default: + goto pool32f_invalid; + } + break; + case MADDF_FMT: + check_insn(ctx, ISA_MIPS32R6); + switch (ctx->opcode >> 9 & 0x3) { + case FMT_SDPS_S: + mips32_op = OPC_MADDF_S; + goto do_fpop; + case FMT_SDPS_D: + mips32_op = OPC_MADDF_D; + goto do_fpop; + default: + goto pool32f_invalid; + } + break; + case MSUBF_FMT: + check_insn(ctx, ISA_MIPS32R6); + switch (ctx->opcode >> 9 & 0x3) { + case FMT_SDPS_S: + mips32_op = OPC_MSUBF_S; + goto do_fpop; + case FMT_SDPS_D: + mips32_op = OPC_MSUBF_D; + goto do_fpop; + default: + goto pool32f_invalid; + } + break; default: goto pool32f_invalid; }

[09/13] target-mips: microMIPS32 R6 POOL32F instructions

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