From patchwork Wed Jun 3 21:17:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 480231 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6A257140157 for ; Thu, 4 Jun 2015 07:19:50 +1000 (AEST) Received: from localhost ([::1]:38284 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0G4i-0002JB-Fo for incoming@patchwork.ozlabs.org; Wed, 03 Jun 2015 17:19:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34664) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0G2B-00062k-Ca for qemu-devel@nongnu.org; Wed, 03 Jun 2015 17:17:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0G26-0002Km-Rc for qemu-devel@nongnu.org; Wed, 03 Jun 2015 17:17:11 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:40171) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0G26-0002Kb-Kp for qemu-devel@nongnu.org; Wed, 03 Jun 2015 17:17:06 -0400 Received: from weber.rr44.fr ([2001:470:d4ed:0:7e05:7ff:fe0d:f152]) by hall.aurel32.net with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84) (envelope-from ) id 1Z0G25-0003uR-Rl; Wed, 03 Jun 2015 23:17:06 +0200 Received: from aurel32 by weber.rr44.fr with local (Exim 4.85) (envelope-from ) id 1Z0G25-00029E-3i; Wed, 03 Jun 2015 23:17:05 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 3 Jun 2015 23:17:00 +0200 Message-Id: <1433366220-8214-1-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 2.1.4 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:101::1 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH] sh4/r2d: convert to new MMIO accessor style X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The documentation is clear to use 16-bit accesses for all registers. Signed-off-by: Aurelien Jarno --- hw/sh4/r2d.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 4221060..5e22ed7 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -127,7 +127,7 @@ static void r2d_fpga_irq_set(void *opaque, int n, int level) update_irl(fpga); } -static uint32_t r2d_fpga_read(void *opaque, hwaddr addr) +static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size) { r2d_fpga_t *s = opaque; @@ -146,7 +146,7 @@ static uint32_t r2d_fpga_read(void *opaque, hwaddr addr) } static void -r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value) +r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size) { r2d_fpga_t *s = opaque; @@ -170,10 +170,10 @@ r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value) } static const MemoryRegionOps r2d_fpga_ops = { - .old_mmio = { - .read = { r2d_fpga_read, r2d_fpga_read, NULL, }, - .write = { r2d_fpga_write, r2d_fpga_write, NULL, }, - }, + .read = r2d_fpga_read, + .write = r2d_fpga_write, + .impl.min_access_size = 2, + .impl.max_access_size = 2, .endianness = DEVICE_NATIVE_ENDIAN, };