From patchwork Wed May 27 13:29:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongbok Kim X-Patchwork-Id: 477121 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 60EDB14027C for ; Wed, 27 May 2015 23:32:47 +1000 (AEST) Received: from localhost ([::1]:53980 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxbRt-00070s-Jn for incoming@patchwork.ozlabs.org; Wed, 27 May 2015 09:32:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60849) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxbPl-0003NJ-1Q for qemu-devel@nongnu.org; Wed, 27 May 2015 09:30:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YxbPb-0004tI-RX for qemu-devel@nongnu.org; Wed, 27 May 2015 09:30:32 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:13527) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxbPb-0004oE-Lt for qemu-devel@nongnu.org; Wed, 27 May 2015 09:30:23 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 5C3CB4B9758D9; Wed, 27 May 2015 14:30:17 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 27 May 2015 14:30:13 +0100 Received: from localhost.localdomain (192.168.14.192) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.224.2; Wed, 27 May 2015 14:30:13 +0100 From: Yongbok Kim To: Date: Wed, 27 May 2015 14:29:01 +0100 Message-ID: <1432733342-64176-3-git-send-email-yongbok.kim@imgtec.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1432733342-64176-1-git-send-email-yongbok.kim@imgtec.com> References: <1432733342-64176-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.192] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: peter.maydell@linaro.org, leon.alrae@imgtec.com, afaerber@suse.de, rth@twiddle.net Subject: [Qemu-devel] [PATCH v6 2/3] softmmu: Add probe_write() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add probe_write() in order to support such functionality that probes if a specified guest virtual address exists in TLB and is writable. The function forces a tlb_fill() if the address does not exist or is not writable, as a result an exception can occur. Signed-off-by: Yongbok Kim --- include/exec/exec-all.h | 2 ++ softmmu_template.h | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b58cd47..af51203 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -109,6 +109,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, hwaddr paddr, MemTxAttrs attrs, int prot, int mmu_idx, target_ulong size); void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); +void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, + uintptr_t retaddr); #else static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) { diff --git a/softmmu_template.h b/softmmu_template.h index 9cb1659..1558b8b 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -548,6 +548,24 @@ glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr, helper_te_st_name(env, addr, val, oi, GETRA()); } +#if DATA_SIZE == 1 +/* Probe if the specified guest virtual address exists in TLB and is writable, + if not force a tlb_fill(). As a result an exception can occur. */ +void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, + uintptr_t retaddr) +{ + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; + + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + /* TLB entry is for a different page */ + if (!VICTIM_TLB_HIT(addr_write)) { + tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); + } + } +} +#endif #endif /* !defined(SOFTMMU_CODE_ACCESS) */ #undef READ_ACCESS_TYPE