From patchwork Sun May 24 10:51:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 475963 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B50C01402B9 for ; Sun, 24 May 2015 20:51:41 +1000 (AEST) Received: from localhost ([::1]:39706 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwTVL-0008Kk-J1 for incoming@patchwork.ozlabs.org; Sun, 24 May 2015 06:51:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58435) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwTUi-00074Y-3W for qemu-devel@nongnu.org; Sun, 24 May 2015 06:51:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YwTUe-0008W4-79 for qemu-devel@nongnu.org; Sun, 24 May 2015 06:51:00 -0400 Received: from mail-lb0-f172.google.com ([209.85.217.172]:36568) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwTUd-0008Vy-Tk for qemu-devel@nongnu.org; Sun, 24 May 2015 06:50:56 -0400 Received: by lbbqq2 with SMTP id qq2so36963513lbb.3 for ; Sun, 24 May 2015 03:50:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ELRpoToQgZXnpBQfNdTUSrqmbcMZfjRAA0UXFWePQpU=; b=B52JZGQpkEnaFO6FUiV7cvG4dAIC4CpQeiT5GkwamEzN65rbVrP+VTHNazIpNYZdar 00JkKlAi/vVkygMFAH8Lskz0KY7popRA5y/vbBw5RJ/wBQSnql7DX6XyX46DirYfo36D IhrOUVG9LbxAto01O75ILawVFdNWGL68BVMJiLMypdycou7PlN80PbGEVAIG26jYKDYb 8m+Ftg1yRC6FB2VWJ7OBuKAfzVManPXk1B2bwMK6urAH3pCTB0IedsWQEVxDOeR9fBZv yy1wmurkwyvWa/zQSIhG38E+vK1UCkZwvMx/vcjpLi7gQOikLFLdznYqIeWH7M5XmtOH 1mIw== X-Gm-Message-State: ALoCoQnZP1wEweowyDbA5MU3jqHjxht5NaD2mNXWVg6avEtm1RpDzcnnYELqAzOuCzBNBLMUY1jw X-Received: by 10.152.8.6 with SMTP id n6mr13898635laa.116.1432464655200; Sun, 24 May 2015 03:50:55 -0700 (PDT) Received: from localhost.localdomain (188-178-240-98-static.dk.customer.tdc.net. [188.178.240.98]) by mx.google.com with ESMTPSA id am7sm1689944lbc.3.2015.05.24.03.50.53 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 24 May 2015 03:50:54 -0700 (PDT) From: Christoffer Dall To: qemu-devel@nongnu.org Date: Sun, 24 May 2015 12:51:06 +0200 Message-Id: <1432464666-4825-5-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 2.1.2.330.g565301e.dirty In-Reply-To: <1432464666-4825-1-git-send-email-christoffer.dall@linaro.org> References: <1432464666-4825-1-git-send-email-christoffer.dall@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.217.172 Cc: kvmarm@lists.cs.columbia.edu, Christoffer Dall , eric.auger@linaro.org Subject: [Qemu-devel] [PATCH v3 4/4] target-arm: Add the GICv2m to the virt board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a GICv2m device to the virt board to enable MSIs on the generic PCI host controller. We allocate 64 SPIs in the IRQ space for now (this can be increased/decreased later) and map the GICv2m right after the GIC in the memory map. Signed-off-by: Christoffer Dall Reviewed-by: Eric Auger --- Changes since v2: - Factored out changes to GIC DT node to previous patch. - Renamed QOM type name to "arm-gicv2m" Changes since v1: - Remove stray merge conflict line - Reworded commmit message. hw/arm/virt.c | 42 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 6797c6f..2972bb3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -45,6 +45,7 @@ #include "hw/pci-host/gpex.h" #define NUM_VIRTIO_TRANSPORTS 32 +#define NUM_GICV2M_SPIS 64 /* Number of external interrupt lines to configure the GIC with */ #define NUM_IRQS 128 @@ -71,6 +72,7 @@ enum { VIRT_RTC, VIRT_FW_CFG, VIRT_PCIE, + VIRT_GIC_V2M, }; typedef struct MemMapEntry { @@ -88,6 +90,7 @@ typedef struct VirtBoardInfo { int fdt_size; uint32_t clock_phandle; uint32_t gic_phandle; + uint32_t v2m_phandle; } VirtBoardInfo; typedef struct { @@ -127,6 +130,7 @@ static const MemMapEntry a15memmap[] = { /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, + [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, [VIRT_UART] = { 0x09000000, 0x00001000 }, [VIRT_RTC] = { 0x09010000, 0x00001000 }, [VIRT_FW_CFG] = { 0x09020000, 0x0000000a }, @@ -148,6 +152,7 @@ static const int a15irqmap[] = { [VIRT_RTC] = 2, [VIRT_PCIE] = 3, /* ... to 6 */ [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ + [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ }; static VirtBoardInfo machines[] = { @@ -323,9 +328,21 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) } } -static void fdt_add_gic_node(VirtBoardInfo *vbi) +static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi) { + vbi->v2m_phandle = qemu_fdt_alloc_phandle(vbi->fdt); + qemu_fdt_add_subnode(vbi->fdt, "/intc/v2m"); + qemu_fdt_setprop_string(vbi->fdt, "/intc/v2m", "compatible", + "arm,gic-v2m-frame"); + qemu_fdt_setprop(vbi->fdt, "/intc/v2m", "msi-controller", NULL, 0); + qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/v2m", "reg", + 2, vbi->memmap[VIRT_GIC_V2M].base, + 2, vbi->memmap[VIRT_GIC_V2M].size); + qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->v2m_phandle); +} +static void fdt_add_gic_node(VirtBoardInfo *vbi) +{ vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt); qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle); @@ -347,6 +364,25 @@ static void fdt_add_gic_node(VirtBoardInfo *vbi) } +static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic) +{ + int i; + int irq = vbi->irqmap[VIRT_GIC_V2M]; + DeviceState *dev; + + dev = qdev_create(NULL, "arm-gicv2m"); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_V2M].base); + qdev_prop_set_uint32(dev, "base-spi", irq); + qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); + qdev_init_nofail(dev); + + for (i = 0; i < NUM_GICV2M_SPIS; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + } + + fdt_add_v2m_gic_node(vbi); +} + static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic) { /* We create a standalone GIC v2 */ @@ -397,6 +433,8 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic) } fdt_add_gic_node(vbi); + + create_v2m(vbi, pic); } static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic) @@ -707,6 +745,8 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic) qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0, nr_pcie_buses - 1); + qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent", vbi->v2m_phandle); + qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 2, base_ecam, 2, size_ecam); qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",