From patchwork Fri May 22 08:22:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 475318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 348281402ED for ; Fri, 22 May 2015 18:23:58 +1000 (AEST) Received: from localhost ([::1]:60839 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YviFI-0003kk-7z for incoming@patchwork.ozlabs.org; Fri, 22 May 2015 04:23:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48049) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YviEe-0002el-Fs for qemu-devel@nongnu.org; Fri, 22 May 2015 04:23:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YviEZ-0005NS-3E for qemu-devel@nongnu.org; Fri, 22 May 2015 04:23:16 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:45730) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YviEY-0005MN-QG for qemu-devel@nongnu.org; Fri, 22 May 2015 04:23:10 -0400 From: Bastian Koppelmann To: qemu-devel@nongnu.org Date: Fri, 22 May 2015 10:22:57 +0200 Message-Id: <1432282979-24500-9-git-send-email-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.4.1 In-Reply-To: <1432282979-24500-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1432282979-24500-1-git-send-email-kbastian@mail.uni-paderborn.de> X-IMT-Spam-Score: 0.0 () X-PMX-Version: 6.2.0.2453472, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2015.5.22.81216 X-IMT-Authenticated-Sender: uid=kbastian,ou=People,o=upb,c=de X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Cc: rth@twiddle.net Subject: [Qemu-devel] [PATCH v2 08/10] target-tricore: add FCALL instructions of the v1.6 ISA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Bastian Koppelmann --- v1 -> v2: - gen_fcall_save_ctx now uses a temp for the a[10] register, so this does not get updated if the store traps. target-tricore/translate.c | 26 ++++++++++++++++++++++++++ target-tricore/tricore-opcodes.h | 3 +++ 2 files changed, 29 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 4aea0c6..76bab8e 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3275,6 +3275,18 @@ static void gen_loop(DisasContext *ctx, int r1, int32_t offset) gen_goto_tb(ctx, 0, ctx->next_pc); } +static void gen_fcall_save_ctx(DisasContext *ctx) +{ + TCGv temp = tcg_temp_new(); + + tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); + tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_mov_tl(cpu_gpr_a[10], temp); + + tcg_temp_free(temp); +} + static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, int r2 , int32_t constant , int32_t offset) { @@ -3369,6 +3381,14 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, gen_helper_1arg(call, ctx->next_pc); gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; + case OPC1_32_B_FCALL: + gen_fcall_save_ctx(ctx); + gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + break; + case OPC1_32_B_FCALLA: + gen_fcall_save_ctx(ctx); + gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); + break; case OPC1_32_B_JLA: tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); /* fall through */ @@ -6311,6 +6331,10 @@ static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) gen_helper_1arg(call, ctx->next_pc); tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; + case OPC2_32_RR_FCALLI: + gen_fcall_save_ctx(ctx); + tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); + break; } tcg_gen_exit_tb(0); ctx->bstate = BS_BRANCH; @@ -7946,6 +7970,8 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) /* B-format */ case OPC1_32_B_CALL: case OPC1_32_B_CALLA: + case OPC1_32_B_FCALL: + case OPC1_32_B_FCALLA: case OPC1_32_B_J: case OPC1_32_B_JA: case OPC1_32_B_JL: diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index d1506a9..bb1939c 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -428,6 +428,8 @@ enum { /* B Format */ OPC1_32_B_CALL = 0x6d, OPC1_32_B_CALLA = 0xed, + OPC1_32_B_FCALL = 0x61, + OPC1_32_B_FCALLA = 0xe1, OPC1_32_B_J = 0x1d, OPC1_32_B_JA = 0x9d, OPC1_32_B_JL = 0x5d, @@ -1127,6 +1129,7 @@ enum { OPC2_32_RR_JI = 0x03, OPC2_32_RR_JLI = 0x02, OPC2_32_RR_CALLI = 0x00, + OPC2_32_RR_FCALLI = 0x01, }; /* * RR1 Format