From patchwork Wed Apr 15 16:02:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 461588 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2E40F1401DE for ; Thu, 16 Apr 2015 02:10:38 +1000 (AEST) Received: from localhost ([::1]:33013 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiPtb-00067H-N4 for incoming@patchwork.ozlabs.org; Wed, 15 Apr 2015 12:10:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52297) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiPmb-0002dI-Sj for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YiPmZ-0001zC-1d for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:21 -0400 Received: from mail-ob0-f170.google.com ([209.85.214.170]:34772) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiPmY-0001z6-UA for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:19 -0400 Received: by obfe9 with SMTP id e9so25436608obf.1 for ; Wed, 15 Apr 2015 09:03:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Q6gqRS2iQrMA5LIERTM3sC6JIzrp+MGb6bRPbAGziXA=; b=OiHuvloRSkU3Z0WxXt5uUIYjoYlFKpkp2cmGjo3cgO5XK0SDj2JHW6gzwYVh0XFJta 1/Kn64skTtYthwlXltfaCyb6yCpbcxVPhvf7W7xxot67iRDY0NEpINcF202/WA5iGwat JyccT9Tf1ueBZM+wnFIVbHMAiT2tolpyhpgre1kbzP5Un2U4yHF1VYpXHa1M2A/hhXJB itjzo/TJ5GlvmVPjs3b+yLd4JQm/HEAqfAIKWJ87T9R53pPmDLjpHKvhk0gKyxQVHmDB 4saTpoQjbwv18JByJu2AXeYC28EiESHLEN+YaJ3cYfW0exi6gJm9lfxTGvOFF4GTiP9N nzhA== X-Gm-Message-State: ALoCoQniPqiPqeFc1fxgomx43G/XNI+waGudR9Urupa9tfjspy5oeIFZGBtW0WRuTN9sKALBq3dS X-Received: by 10.182.110.193 with SMTP id ic1mr18377468obb.59.1429113770694; Wed, 15 Apr 2015 09:02:50 -0700 (PDT) Received: from gbellows-linaro.gateway.pace.com (99-179-1-214.lightspeed.austtx.sbcglobal.net. [99.179.1.214]) by mx.google.com with ESMTPSA id x142sm2567707oie.19.2015.04.15.09.02.48 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 15 Apr 2015 09:02:49 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 15 Apr 2015 11:02:17 -0500 Message-Id: <1429113742-8371-12-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> References: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.170 Cc: Fabian Aggeler , Greg Bellows Subject: [Qemu-devel] [PATCH v3 11/16] hw/intc/arm_gic: Handle grouping for GICC_HPPIR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Grouping (GICv2) and Security Extensions change the behaviour of reads of the highest priority pending interrupt register (ICCHPIR/GICC_HPPIR). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- hw/intc/arm_gic.c | 29 ++++++++++++++++++++++++++++- hw/intc/gic_internal.h | 1 + 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index e65a271..d6f8dae 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -329,6 +329,33 @@ uint8_t gic_get_running_priority(GICState *s, int cpu) } } +uint16_t gic_get_current_pending_irq(GICState *s, int cpu) +{ + bool isGrp0; + uint16_t pendingId = s->current_pending[cpu]; + + if (pendingId < GIC_MAXIRQ && (s->revision >= 2 || s->security_extn)) { + isGrp0 = GIC_TEST_GROUP0(pendingId, (1 << cpu)); + if ((isGrp0 && !s->enabled_grp[0]) + || (!isGrp0 && !s->enabled_grp[1])) { + return 1023; + } + if (s->security_extn) { + if (isGrp0 && ns_access()) { + /* Group0 interrupts hidden from Non-secure access */ + return 1023; + } + if (!isGrp0 && !ns_access() + && !(s->cpu_control[cpu][0] & GICC_CTLR_S_ACK_CTL)) { + /* Group1 interrupts only seen by Secure access if + * AckCtl bit set. */ + return 1022; + } + } + } + return pendingId; +} + void gic_complete_irq(GICState *s, int cpu, int irq) { int update = 0; @@ -867,7 +894,7 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) case 0x14: /* Running Priority */ return gic_get_running_priority(s, cpu); case 0x18: /* Highest Pending Interrupt */ - return s->current_pending[cpu]; + return gic_get_current_pending_irq(s, cpu); case 0x1c: /* Aliased Binary Point */ if (!s->security_extn || (s->security_extn && ns_access())) { /* If Security Extensions are present ABPR is a secure register, diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 821ce16..fbb1f66 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -79,6 +79,7 @@ void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); uint32_t gic_get_cpu_control(GICState *s, int cpu); void gic_set_cpu_control(GICState *s, int cpu, uint32_t value); uint8_t gic_get_running_priority(GICState *s, int cpu); +uint16_t gic_get_current_pending_irq(GICState *s, int cpu); static inline bool gic_test_pending(GICState *s, int irq, int cm)