From patchwork Fri Mar 27 19:10:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 455556 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D8FFB14007F for ; Sat, 28 Mar 2015 06:17:53 +1100 (AEDT) Received: from localhost ([::1]:51478 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YbZlP-00030I-PY for incoming@patchwork.ozlabs.org; Fri, 27 Mar 2015 15:17:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50330) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YbZfN-0001kb-QW for qemu-devel@nongnu.org; Fri, 27 Mar 2015 15:12:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YbZf0-0005HN-Dj for qemu-devel@nongnu.org; Fri, 27 Mar 2015 15:11:37 -0400 Received: from mail-oi0-f49.google.com ([209.85.218.49]:34776) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YbZf0-0005HB-9g for qemu-devel@nongnu.org; Fri, 27 Mar 2015 15:11:14 -0400 Received: by oigz129 with SMTP id z129so39311347oig.1 for ; Fri, 27 Mar 2015 12:11:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=313ibmLBM6bQu+rLv96VB0+DJ5ste/f7FCoj7qYlPMY=; b=LzzoC2lptYmruT6FWfqvx2R/rx6jQSRQnbkbuAqNBkUqAf5TqyWiTdLsHiohCRgAf4 K5o/vwniTXBEh80580INB02ugXUqVq26n5g/be16F4zVcJol2vqhN63nIJgfbQ/g4DZC GPtbC05AJPUurxh68rz3h8kc7VTzjnSDY1l93l6dODSEu19lzX7f5ZrF891Cahu+QrZQ 4vcoslqh8QxdYYCNjIvsI8p9jUkNfgJiMkLHed2I/qs39BEyzQaxiEiAc5lrduuLarxj KM89vKSRiEhf4WaDo63uSRpy1VtDGtFKrMdvTr0Q6NtPZCgqzcYpspIzkn7lPTgRm454 RuCg== X-Gm-Message-State: ALoCoQnE/0oFka0n5z/mIwBjINt+9kIaZGHSHkcmLz8VNBJAtRDtCKdo08bJJeFyGPR+RAOVIFzF X-Received: by 10.60.16.168 with SMTP id h8mr17382567oed.4.1427483473887; Fri, 27 Mar 2015 12:11:13 -0700 (PDT) Received: from gbellows-linaro.bellowshome.netattlocal.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id hc7sm1490859obb.16.2015.03.27.12.11.12 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 27 Mar 2015 12:11:13 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Date: Fri, 27 Mar 2015 14:10:46 -0500 Message-Id: <1427483446-31900-8-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1427483446-31900-1-git-send-email-greg.bellows@linaro.org> References: <1427483446-31900-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.218.49 Cc: Greg Bellows Subject: [Qemu-devel] [[PATCH] 7/7] target-arm: Add WFx instruction trap support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add support for trapping WFI and WFE instructions to the proper EL when SCTLR/SCR/HCR settings apply. Signed-off-by: Greg Bellows --- target-arm/op_helper.c | 75 +++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 71 insertions(+), 4 deletions(-) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index aa175b5..d7e734d 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -209,23 +209,90 @@ uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift) return res; } +static inline uint32_t check_wfx_trap(CPUARMState *env, bool is_wfe) +{ + int cur_el = arm_current_el(env), el; + uint32_t target_el = 0; + uint64_t mask; + + /* Check whether any EL controls above us trap WFx instructions */ + for (el = cur_el + 1; el <= 3; el++) { + switch (el) { + case 1: + mask = (is_wfe) ? SCTLR_nTWE : SCTLR_nTWI; + /* Secure EL1 is only valid in AArch64. If EL0 is AArch64 then so + * must be EL1. + */ + if (arm_el_is_aa64(env, 1)) { + if ((env->cp15.sctlr_el[1] & mask) == 0) { + target_el = el; + } + } else if (arm_feature(env, ARM_FEATURE_V8) && + !arm_is_secure(env)) { + /* SCTLR WFx SCTLR trap bits only exist in ARMv8 */ + if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & mask) == 0) { + target_el = el; + } + } + break; + case 2: + if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure(env)) { + mask = (is_wfe) ? HCR_TWE : HCR_TWI; + if ((env->cp15.hcr_el2 & mask) == mask) { + target_el = el; + } + } + break; + case 3: + if (arm_feature(env, ARM_FEATURE_EL3) && + arm_feature(env, ARM_FEATURE_V8)) { + mask = (is_wfe) ? SCR_TWE : SCR_TWI; + if ((env->cp15.scr_el3 & mask) == mask) { + target_el = el; + } + } + break; + } + } + + return target_el; +} + void HELPER(wfi)(CPUARMState *env) { CPUState *cs = CPU(arm_env_get_cpu(env)); - - cs->exception_index = EXCP_HLT; - cs->halted = 1; + uint32_t target_el = 0; + + target_el = check_wfx_trap(env, false); + if (target_el) { + cs->exception_index = EXCP_UDEF; + env->exception.syndrome = syn_wfx(1, 0xe, false); + env->exception.target_el = target_el; + env->pc -= 4; + } else { + cs->exception_index = EXCP_HLT; + cs->halted = 1; + } cpu_loop_exit(cs); } void HELPER(wfe)(CPUARMState *env) { CPUState *cs = CPU(arm_env_get_cpu(env)); + uint32_t target_el = 0; /* Don't actually halt the CPU, just yield back to top * level loop */ - cs->exception_index = EXCP_YIELD; + target_el = check_wfx_trap(env, true); + if (target_el) { + cs->exception_index = EXCP_UDEF; + env->exception.syndrome = syn_wfx(1, 0xe, true); + env->exception.target_el = target_el; + env->pc -= 4; + } else { + cs->exception_index = EXCP_YIELD; + } cpu_loop_exit(cs); }