@@ -687,13 +687,8 @@ static void ahci_test_identify(AHCIQState *ahci)
i = ahci_port_select(ahci);
g_test_message("Selected port %u for test", i);
- /* Clear out this port's interrupts (ignore the init register d2h fis) */
- reg = ahci_px_rreg(ahci, i, AHCI_PX_IS);
- ahci_px_wreg(ahci, i, AHCI_PX_IS, reg);
- g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0);
-
- /* Wipe the FIS-Receive Buffer */
- qmemset(ahci->port[i].fb, 0x00, 0x100);
+ /* Clear out the FIS Receive area and any pending interrupts. */
+ ahci_port_clear(ahci, i);
/* Create a Command Table buffer. 0x80 is the smallest with a PRDTL of 0. */
/* We need at least one PRD, so round up to the nearest 0x80 multiple. */
@@ -294,3 +294,19 @@ unsigned ahci_port_select(AHCIQState *ahci)
g_assert(i < 32);
return i;
}
+
+/**
+ * Clear a port's interrupts and status information prior to a test.
+ */
+void ahci_port_clear(AHCIQState *ahci, uint8_t port)
+{
+ uint32_t reg;
+
+ /* Clear out this port's interrupts (ignore the init register d2h fis) */
+ reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
+ ahci_px_wreg(ahci, port, AHCI_PX_IS, reg);
+ g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
+
+ /* Wipe the FIS-Recieve Buffer */
+ qmemset(ahci->port[port].fb, 0x00, 0x100);
+}
@@ -432,5 +432,6 @@ void ahci_pci_enable(AHCIQState *ahci);
void start_ahci_device(AHCIQState *ahci);
void ahci_hba_enable(AHCIQState *ahci);
unsigned ahci_port_select(AHCIQState *ahci);
+void ahci_port_clear(AHCIQState *ahci, uint8_t port);
#endif