From patchwork Fri Jan 23 16:17:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 432212 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 37DCE14029E for ; Sat, 24 Jan 2015 03:18:15 +1100 (AEDT) Received: from localhost ([::1]:60168 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEgw1-0006it-DD for incoming@patchwork.ozlabs.org; Fri, 23 Jan 2015 11:18:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38726) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEgvQ-0005lA-V8 for qemu-devel@nongnu.org; Fri, 23 Jan 2015 11:17:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YEgvM-00035t-DC for qemu-devel@nongnu.org; Fri, 23 Jan 2015 11:17:36 -0500 Received: from mail-pa0-f50.google.com ([209.85.220.50]:53055) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEgvM-00035l-7b for qemu-devel@nongnu.org; Fri, 23 Jan 2015 11:17:32 -0500 Received: by mail-pa0-f50.google.com with SMTP id rd3so8628068pab.9 for ; Fri, 23 Jan 2015 08:17:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0tXI1QMavhgz8mME/IjZDrQqAYTV2h+zL62AI/BkYCw=; b=aDd+b+xemRIOMWgN3dSxmTxrXgAl7d/8x8a97GpwqExoHGC0ZlUChohqtkHUwhGH3R d8U3ag/S7tE+6cgH0/bhuWNfswwy+CnUktkGCmucJXNmWRNGifK7foxER7DSRCQ1mXgn 4U9rtV/QPCkCQv2vLb18hrIF57aryRRhMcF2z5pcCrP9dxcCuxg9DXEKtGicGwrCzEkn bC0bQpDDMpaPhwWOdFx4v+8dujwpzOLCSvfW47S41DH5utn6wzUZ2DWpyOXksJ/thjBp 84EiNI5v5uWXHE3glLJLjUVpI55KjJQC7j0k3u/IH6Y96Sjd4pWwKSvnKQhiZKUfw7MM dXIQ== X-Gm-Message-State: ALoCoQlr2yIxweQw/SPUJt3Al/lKAUssWToJE0tF6a1Kc+I1Ce71PWskfjxsz+LXF7JXEqb+oMlB X-Received: by 10.66.65.234 with SMTP id a10mr12795509pat.120.1422029851653; Fri, 23 Jan 2015 08:17:31 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id s4sm643214pdd.40.2015.01.23.08.17.30 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 23 Jan 2015 08:17:31 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 23 Jan 2015 10:17:15 -0600 Message-Id: <1422029835-4696-5-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1422029835-4696-1-git-send-email-greg.bellows@linaro.org> References: <1422029835-4696-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.50 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH V2 4/4] target-arm: Add missing SP_ELx register definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added CP register definitions for SP_EL1 and SP_EL2. Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v1 -> v2 - Remove unnecessary accessfn for SP_EL1/2 - Revert SP_EL0 accessfn name to sp_el0_access --- target-arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 29f3b62..79c54a9 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .access = PL1_RW, .accessfn = sp_el0_access, .type = ARM_CP_NO_MIGRATE, .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, + { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, { .name = "SPSel", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, .type = ARM_CP_NO_MIGRATE, @@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .access = PL2_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), .resetvalue = 0 }, + { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, + .access = PL3_RW, .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, REGINFO_SENTINEL };