From patchwork Fri Jan 23 14:49:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 432189 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8FB47140151 for ; Sat, 24 Jan 2015 01:52:51 +1100 (AEDT) Received: from localhost ([::1]:59561 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEfbN-0004Zb-LQ for incoming@patchwork.ozlabs.org; Fri, 23 Jan 2015 09:52:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42892) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEfYO-0000La-Fq for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YEfYK-0005Iu-Mi for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:44 -0500 Received: from mail-pd0-f171.google.com ([209.85.192.171]:35282) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEfYK-0005Ia-Hn for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:40 -0500 Received: by mail-pd0-f171.google.com with SMTP id fp1so8934558pdb.2 for ; Fri, 23 Jan 2015 06:49:40 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YDAMqvRXFPxdH4HDxTd2Ywp5/6Q36OjSIbAs/pS/BRo=; b=TWDONqqPz0OQ1UbTIq+qkQpf9TIK9AaQ9ZNwqSWGGHrCnAkdo9huY4mzVmhLlS0+gf jg7F1a5ga07qsEMnWyaxTKua8lvfTZAbUyRn+PRCFMuVbQzqY1Cd57dGkLv2BhyYjBsX 8J4F1KBl2V8L8hY/t0U+yWamoqILd2KCNW0h3aZ+hvT2gf7NkRjEsmOXJ/vTzCt6KDGY dwWGc2uIFc6wMcrUPLBxGzLNxcaawuEuNBeeE+R3XTZuMfRsdi8j1Vk+6c18ZcOFLzXo IANfLIOuSvMvhfi6N9bK0VUUyNM/6UJoR/JJRTrboGFHdKB0L7DnczIO6U5YpfvO9L7O +e/A== X-Gm-Message-State: ALoCoQmFmtdW8ZaLVFfathO2UvTiHtBzRN4G82i4TYF3Ob4wTF1he/NQGQV2qf1p5Jpx+1WRF3Tl X-Received: by 10.66.255.99 with SMTP id ap3mr11628026pad.55.1422024580035; Fri, 23 Jan 2015 06:49:40 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id oc7sm2146455pdb.68.2015.01.23.06.49.38 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 23 Jan 2015 06:49:39 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 23 Jan 2015 08:49:23 -0600 Message-Id: <1422024563-27096-5-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1422024563-27096-1-git-send-email-greg.bellows@linaro.org> References: <1422024563-27096-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.171 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH 4/4] target-arm: Add missing SP_ELx register definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added CP register definitions for SP_EL1 and SP_EL2. Signed-off-by: Greg Bellows --- target-arm/helper.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index d5f0997..ae7394d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2096,7 +2096,7 @@ static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) return cpu->dcz_blocksize | dzp_bit; } -static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) +static CPAccessResult sp_el_access(CPUARMState *env, const ARMCPRegInfo *ri) { if (!(env->pstate & PSTATE_SP)) { /* Access to SP_EL0 is undefined if it's being used as @@ -2326,9 +2326,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { */ { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, - .access = PL1_RW, .accessfn = sp_el0_access, + .access = PL1_RW, .accessfn = sp_el_access, .type = ARM_CP_NO_MIGRATE, .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, + { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, + .access = PL2_RW, .accessfn = sp_el_access, + .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, { .name = "SPSel", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, .type = ARM_CP_NO_MIGRATE, @@ -2410,6 +2415,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .access = PL2_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), .resetvalue = 0 }, + { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, + .access = PL3_RW, .accessfn = sp_el_access, + .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, REGINFO_SENTINEL };