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[3/4] target-tricore: Add instructions of RRPW opcode format

Message ID 1421863489-7716-4-git-send-email-kbastian@mail.uni-paderborn.de
State New
Headers show

Commit Message

Bastian Koppelmann Jan. 21, 2015, 6:04 p.m. UTC 
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

Comments

Richard Henderson Jan. 21, 2015, 6:57 p.m. UTC | #1 
On 01/21/2015 10:04 AM, Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
>  target-tricore/translate.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
> 
> diff --git a/target-tricore/translate.c b/target-tricore/translate.c
> index 4af31c2..73d8d7d 100644
> --- a/target-tricore/translate.c
> +++ b/target-tricore/translate.c
> @@ -5084,6 +5084,53 @@ static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
>      }
>  }
>  
> +/* RRPW format */
> +static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
> +{
> +    uint32_t op2;
> +    int r1, r2, r3;
> +    int32_t pos, width;
> +
> +    op2 = MASK_OP_RRPW_OP2(ctx->opcode);
> +    r1 = MASK_OP_RRPW_S1(ctx->opcode);
> +    r2 = MASK_OP_RRPW_S2(ctx->opcode);
> +    r3 = MASK_OP_RRPW_D(ctx->opcode);
> +    pos = MASK_OP_RRPW_POS(ctx->opcode);
> +    width = MASK_OP_RRPW_WIDTH(ctx->opcode);
> +
> +    switch (op2) {
> +    case OPC2_32_RRPW_EXTR:
> +        if (pos + width <= 31) {
> +            tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
> +            tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32 - width));
> +            /* sign extend it */
> +            tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], (32 - width));
> +            tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], (32 - width));

You can do this with just the last two shifts:

  shl tmp, r3, 32 - pos - width
  sar r3, tmp, 32 - width

Given that this appears to be the canonical way to sign-extend,
you may well want to special case pos == 0, width == {8,16} to
emit the tcg extension opcodes.


> +        temp = tcg_temp_new();
> +        tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], const16);
> +        tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 32 - const16);
> +        tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
> +        tcg_temp_free(temp);
> +        break;

It should be worth special casing r1 == r2 as rotate left.


r~
diff mbox

Patch

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 4af31c2..73d8d7d 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -5084,6 +5084,53 @@  static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
     }
 }
 
+/* RRPW format */
+static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
+{
+    uint32_t op2;
+    int r1, r2, r3;
+    int32_t pos, width;
+
+    op2 = MASK_OP_RRPW_OP2(ctx->opcode);
+    r1 = MASK_OP_RRPW_S1(ctx->opcode);
+    r2 = MASK_OP_RRPW_S2(ctx->opcode);
+    r3 = MASK_OP_RRPW_D(ctx->opcode);
+    pos = MASK_OP_RRPW_POS(ctx->opcode);
+    width = MASK_OP_RRPW_WIDTH(ctx->opcode);
+
+    switch (op2) {
+    case OPC2_32_RRPW_EXTR:
+        if (pos + width <= 31) {
+            tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
+            tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32 - width));
+            /* sign extend it */
+            tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], (32 - width));
+            tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], (32 - width));
+        }
+        break;
+    case OPC2_32_RRPW_EXTR_U:
+        if (width == 0) {
+            tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
+        } else {
+            tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
+            tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
+        }
+        break;
+    case OPC2_32_RRPW_IMASK:
+        if (pos + width <= 31) {
+            tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
+            tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
+        }
+        break;
+    case OPC2_32_RRPW_INSERT:
+        if (pos + width <= 31) {
+            tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
+                               width, pos);
+        }
+        break;
+    }
+}
+
 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
 {
     int op1;
@@ -5348,6 +5395,22 @@  static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
     case OPCM_32_RR2_MUL:
         decode_rr2_mul(env, ctx);
         break;
+/* RRPW format */
+    case OPCM_32_RRPW_EXTRACT_INSERT:
+        decode_rrpw_extract_insert(env, ctx);
+        break;
+    case OPC1_32_RRPW_DEXTR:
+        r1 = MASK_OP_RRPW_S1(ctx->opcode);
+        r2 = MASK_OP_RRPW_S2(ctx->opcode);
+        r3 = MASK_OP_RRPW_D(ctx->opcode);
+        const16 = MASK_OP_RRPW_POS(ctx->opcode);
+
+        temp = tcg_temp_new();
+        tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], const16);
+        tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 32 - const16);
+        tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
+        tcg_temp_free(temp);
+        break;
     }
 }