From patchwork Thu Dec 18 00:26:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Morrison X-Patchwork-Id: 422472 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C0E06140082 for ; Thu, 18 Dec 2014 14:39:40 +1100 (AEDT) Received: from localhost ([::1]:52369 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1Rw8-0001K0-Qn for incoming@patchwork.ozlabs.org; Wed, 17 Dec 2014 22:39:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1Oy5-0006sn-O5 for qemu-devel@nongnu.org; Wed, 17 Dec 2014 19:29:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y1Oy0-0007KL-ME for qemu-devel@nongnu.org; Wed, 17 Dec 2014 19:29:25 -0500 Received: from fofx.invlim.com ([71.6.153.225]:49914) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1Oy0-0007Ih-EV; Wed, 17 Dec 2014 19:29:20 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by fofx.invlim.com (Postfix) with ESMTP id 1E74E248288; Wed, 17 Dec 2014 16:19:49 -0800 (PST) X-Virus-Scanned: amavisd-new at example.com Received: from fofx.invlim.com ([127.0.0.1]) by localhost (fofx.invlim.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id zkVznf3SRo5k; Wed, 17 Dec 2014 16:19:47 -0800 (PST) Received: from monster337-linux.localdomain (unknown [10.240.0.46]) by fofx.invlim.com (Postfix) with ESMTP id 7BB4A24827F; Wed, 17 Dec 2014 16:19:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=invlim.com; s=default; t=1418861987; bh=t4z1nOzs9MNkiibX1p4opVRqPiQT+wVVCfg0gWzSY6Q=; h=From:To:Cc:Subject:Date; b=Hiw89tJ1rlwHqSqHh8CfnybQNI+tIx7xGq5L4mU8OTCLiK2GT8XCcJhEJCTSOWGf4 fh+aeHzQwQ0Hf1VbjU0iqIxv4iP0derqgjbf5hlAxmfaOtgTtJakK5ULqFebJtRK08 LkjLIWaM0CCKm9Kd1y/BF/fQejqEDeMJ4+sAoFnc= From: David Morrison To: qemu-devel@nongnu.org, qemu-trivial@nongnu.org, proljc@gmail.com Date: Wed, 17 Dec 2014 16:26:33 -0800 Message-Id: <1418862393-10691-1-git-send-email-dmorrison@invlim.com> X-Mailer: git-send-email 2.1.3 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 71.6.153.225 X-Mailman-Approved-At: Wed, 17 Dec 2014 22:39:18 -0500 Cc: David Morrison Subject: [Qemu-devel] [PATCH] target-openrisc: bugfixes for debugging with GDB+Qemu on OpenRISC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch fixes two bugs in Qemu for OpenRISC, and enables more functionality from or1k-elf-gdb: 1) Fixed the decoding of "system" instructions (starting with 0x2) in dec_sys() in translate.c. In particular, the l.trap instruction is now correctly decoded, which enables for singlestepping and breakpoints to be set in GDB. 2) Fixed a memory read error when debugging kernels inside Qemu and the OpenRISC MMU is enabled Signed-off-by: David R. Morrison --- target-openrisc/cpu.h | 1 + target-openrisc/mmu.c | 2 +- target-openrisc/translate.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 69b96c6..6b08af6 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -20,6 +20,7 @@ #ifndef CPU_OPENRISC_H #define CPU_OPENRISC_H +#define TARGET_HAS_ICE #define TARGET_LONG_BITS 32 #define ELF_MACHINE EM_OPENRISC diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c index 750a936..bbd05f1 100644 --- a/target-openrisc/mmu.c +++ b/target-openrisc/mmu.c @@ -219,7 +219,7 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) hwaddr phys_addr; int prot; - if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) { + if (cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr, 0)) { return -1; } diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 407bd97..d36278f 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1320,7 +1320,7 @@ static void dec_sys(DisasContext *dc, uint32_t insn) #ifdef OPENRISC_DISAS uint32_t K16; #endif - op0 = extract32(insn, 16, 8); + op0 = extract32(insn, 16, 10); #ifdef OPENRISC_DISAS K16 = extract32(insn, 0, 16); #endif