From patchwork Sat Dec 13 16:48:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Antony Pavlov X-Patchwork-Id: 420768 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5A5DC14009B for ; Sun, 14 Dec 2014 03:47:21 +1100 (AEDT) Received: from localhost ([::1]:33607 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xzpqg-0006mU-1m for incoming@patchwork.ozlabs.org; Sat, 13 Dec 2014 11:47:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35676) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzpqA-0006AN-9J for qemu-devel@nongnu.org; Sat, 13 Dec 2014 11:46:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xzppz-0006VD-PW for qemu-devel@nongnu.org; Sat, 13 Dec 2014 11:46:46 -0500 Received: from mail-lb0-x229.google.com ([2a00:1450:4010:c04::229]:45931) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xzppz-0006Us-8G for qemu-devel@nongnu.org; Sat, 13 Dec 2014 11:46:35 -0500 Received: by mail-lb0-f169.google.com with SMTP id p9so7371847lbv.0 for ; Sat, 13 Dec 2014 08:46:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:mime-version:content-type :content-transfer-encoding; bh=dp8YCCJROoAU8Wuxx1llN4JHjkyQn+rgN0LlYyOhwSg=; b=wafGagmImUc1JRVnaO89bj8OUuRHL4CWV7ZwtJ8KyXfeL2SIkFryJnt9aQBOtwO4KT Id6pmzSJmqEIk1IuARYjhN/1mShBD2FBuHaug/RXUNHzN3gn1uwdjC8ZJbddTbMk05We yWzlbFrdYCnf37cGDXpsMQc4wBFDqKKbUpvCKL5jMdgNZ93sBIHvlmvPdwhnQws+Jmsw n6jPX7aagkG9Y9R/yFyvCUDz9R4L/NX0yhA0yav+u9L67IgzJ6DdaXLeDtcVUmkGG09i NUc0C8ZcQUtMWhXh/UogvP/eDiRYGSh+60rtnL/mts13waptbM2DmCqdWQET451rofks CLDg== X-Received: by 10.152.234.169 with SMTP id uf9mr21127766lac.86.1418489194011; Sat, 13 Dec 2014 08:46:34 -0800 (PST) Received: from localhost.localdomain (ppp91-77-198-139.pppoe.mtu-net.ru. [91.77.198.139]) by mx.google.com with ESMTPSA id jf3sm1269264lbc.44.2014.12.13.08.46.32 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 13 Dec 2014 08:46:32 -0800 (PST) From: Antony Pavlov To: qemu-devel@nongnu.org Date: Sat, 13 Dec 2014 19:48:18 +0300 Message-Id: <1418489298-1184-1-git-send-email-antonynpavlov@gmail.com> X-Mailer: git-send-email 2.1.3 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4010:c04::229 Cc: Peter Maydell , Alexander Graf , Blue Swirl , Antony Pavlov , "Edgar E. Iglesias" , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH v4] qemu-log: add log category for MMU info X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Running barebox on qemu-system-mips* with '-d unimp' overloads stderr by very very many mips_cpu_handle_mmu_fault() messages: mips_cpu_handle_mmu_fault address=b80003fd ret 0 physical 00000000180003fd prot 3 mips_cpu_handle_mmu_fault address=a0800884 ret 0 physical 0000000000800884 prot 3 mips_cpu_handle_mmu_fault pc a080cd80 ad b80003fd rw 0 mmu_idx 0 So it's very difficult to find LOG_UNIMP message. The mips_cpu_handle_mmu_fault() messages appear on enabling ANY logging! It's not very handy. Adding separate log category for *_cpu_handle_mmu_fault() logging fixes the problem. Signed-off-by: Antony Pavlov Acked-by: Alexander Graf Reviewed-by: Richard Henderson --- Changes since v3: * rebase over latest 'master'; * add 'Acked-by: Alexander Graf' tag; see http://lists.gnu.org/archive/html/qemu-devel/2014-11/msg01051.html; * drop unicore32; here is gcc 4.9.2 error message: CC unicore32-softmmu/target-unicore32/softmmu.o /home/antony/qemu/target-unicore32/softmmu.c: In function ‘uc32_cpu_handle_mmu_fault’: /home/antony/qemu/target-unicore32/softmmu.c:239:17: error: ‘prot’ may be used uninitialized in this function [-Werror=maybe-uninitialized] qemu_log_mask(CPU_LOG_MMU, ^ /home/antony/qemu/target-unicore32/softmmu.c:239:17: error: ‘phys_addr’ may be used uninitialized in this function [-Werror=maybe-uninitialized] cc1: all warnings being treated as errors Changes since v2: * fix target-ppc/mmu-hash64.c and target-ppc/mmu_helper.c too; * drop LOG_MMU wrapping macros: compile-in qemu_log_mask() always; * use VADDR_PRIx for fixing this microblaze warning: CC microblazeel-softmmu/target-microblaze/helper.o target-microblaze/helper.c: In function ‘mb_cpu_handle_mmu_fault’: target-microblaze/helper.c:83:13: error: format ‘%x’ expects argument of type ‘unsigned int’, \ but argument 4 has type ‘vaddr’ [-Werror=format=] qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%x\n", mmu_idx, address); ^ Changes since v1: * add cris, i386, microblaze, ppc, s390x, sparc and unicore32 support. --- cputlb.c | 3 ++- include/qemu/log.h | 1 + qemu-log.c | 2 ++ target-cris/helper.c | 11 ++++++----- target-i386/helper.c | 15 ++++----------- target-microblaze/helper.c | 8 ++++---- target-mips/helper.c | 6 ++++-- target-ppc/mmu-hash32.c | 18 +++++++++--------- target-ppc/mmu-hash64.c | 18 ++++++++++-------- target-ppc/mmu_helper.c | 26 ++++++++++++++------------ target-s390x/helper.c | 4 ++-- target-sparc/mmu_helper.c | 7 +++---- 12 files changed, 61 insertions(+), 58 deletions(-) diff --git a/cputlb.c b/cputlb.c index a55518a..3b271d4 100644 --- a/cputlb.c +++ b/cputlb.c @@ -270,7 +270,8 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, assert(sz >= TARGET_PAGE_SIZE); #if defined(DEBUG_TLB) - printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, + "tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx " prot=%x idx=%d\n", vaddr, paddr, prot, mmu_idx); #endif diff --git a/include/qemu/log.h b/include/qemu/log.h index d515424..195f665 100644 --- a/include/qemu/log.h +++ b/include/qemu/log.h @@ -40,6 +40,7 @@ static inline bool qemu_log_enabled(void) #define CPU_LOG_RESET (1 << 9) #define LOG_UNIMP (1 << 10) #define LOG_GUEST_ERROR (1 << 11) +#define CPU_LOG_MMU (1 << 12) /* Returns true if a bit is set in the current loglevel mask */ diff --git a/qemu-log.c b/qemu-log.c index 797f2af..05b5493 100644 --- a/qemu-log.c +++ b/qemu-log.c @@ -106,6 +106,8 @@ const QEMULogItem qemu_log_items[] = { "show trace before each executed TB (lots of logs)" }, { CPU_LOG_TB_CPU, "cpu", "show CPU state before block translation" }, + { CPU_LOG_MMU, "mmu", + "log MMU-related activities" }, { CPU_LOG_PCALL, "pcall", "x86 only: show protected mode far calls/returns/exceptions" }, { CPU_LOG_RESET, "cpu_reset", diff --git a/target-cris/helper.c b/target-cris/helper.c index e901c3a..df6c9fd 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -84,8 +84,8 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int r = -1; target_ulong phy; - D(printf("%s addr=%" VADDR_PRIx " pc=%x rw=%x\n", - __func__, address, env->pc, rw)); + qemu_log_mask(CPU_LOG_MMU, "%s addr=%" VADDR_PRIx " pc=%x rw=%x\n", + __func__, address, env->pc, rw); miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK, rw, mmu_idx, 0); if (miss) { @@ -112,9 +112,10 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, r = 0; } if (r > 0) { - D_LOG("%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x" - " pc=%x\n", __func__, r, cs->interrupt_request, address, res.phy, - res.bf_vec, env->pc); + qemu_log_mask(CPU_LOG_MMU, + "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x" + " pc=%x\n", __func__, r, cs->interrupt_request, address, + res.phy, res.bf_vec, env->pc); } return r; } diff --git a/target-i386/helper.c b/target-i386/helper.c index 345bda1..4f1ddf7 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -25,8 +25,6 @@ #include "monitor/monitor.h" #endif -//#define DEBUG_MMU - static void cpu_x86_version(CPUX86State *env, int *family, int *model) { int cpuver = env->cpuid_version; @@ -388,9 +386,7 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state) if (a20_state != ((env->a20_mask >> 20) & 1)) { CPUState *cs = CPU(cpu); -#if defined(DEBUG_MMU) - printf("A20 update: a20=%d\n", a20_state); -#endif + qemu_log_mask(CPU_LOG_MMU, "A20 update: a20=%d\n", a20_state); /* if the cpu is currently executing code, we must unlink it and all the potentially executing TB */ cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); @@ -407,9 +403,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) X86CPU *cpu = x86_env_get_cpu(env); int pe_state; -#if defined(DEBUG_MMU) - printf("CR0 update: CR0=0x%08x\n", new_cr0); -#endif + qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0); if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) != (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) { tlb_flush(CPU(cpu), 1); @@ -452,9 +446,8 @@ void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3) env->cr[3] = new_cr3; if (env->cr[0] & CR0_PG_MASK) { -#if defined(DEBUG_MMU) - printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3); -#endif + qemu_log_mask(CPU_LOG_MMU, + "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3); tlb_flush(CPU(cpu), 0); } } diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 59466c9..32896f4 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -22,7 +22,6 @@ #include "qemu/host-utils.h" #define D(x) -#define DMMU(x) #if defined(CONFIG_USER_ONLY) @@ -75,13 +74,14 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, vaddr = address & TARGET_PAGE_MASK; paddr = lu.paddr + vaddr - lu.vaddr; - DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n", - mmu_idx, vaddr, paddr, lu.prot)); + qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n", + mmu_idx, vaddr, paddr, lu.prot); tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); r = 0; } else { env->sregs[SR_EAR] = address; - DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address)); + qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", + mmu_idx, address); switch (lu.err) { case ERR_PROT: diff --git a/target-mips/helper.c b/target-mips/helper.c index 3a93c20..1b80aa3 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -341,7 +341,8 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, #if 0 log_cpu_state(cs, 0); #endif - qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", + qemu_log_mask(CPU_LOG_MMU, + "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, env->active_tc.PC, address, rw, mmu_idx); /* data access */ @@ -351,7 +352,8 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, access_type = ACCESS_INT; ret = get_physical_address(env, &physical, &prot, address, rw, access_type); - qemu_log("%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, + "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx " prot %d\n", __func__, address, ret, physical, prot); if (ret == TLBRET_MATCH) { diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 0a13a81..dfee358 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -28,10 +28,8 @@ //#define DEBUG_BAT #ifdef DEBUG_MMU -# define LOG_MMU(...) qemu_log(__VA_ARGS__) # define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0) #else -# define LOG_MMU(...) do { } while (0) # define LOG_MMU_STATE(cpu) do { } while (0) #endif @@ -225,7 +223,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, CPUState *cs = CPU(ppc_env_get_cpu(env)); int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS)); - LOG_MMU("direct store...\n"); + qemu_log_mask(CPU_LOG_MMU, "direct store...\n"); if ((sr & 0x1FF00000) >> 20 == 0x07f) { /* Memory-forced I/O controller interface access */ @@ -348,12 +346,13 @@ static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env, ptem = (vsid << 7) | (pgidx >> 10); /* Page address translation */ - LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx + " htab_mask " TARGET_FMT_plx " hash " TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, hash); /* Primary PTEG lookup */ - LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx " vsid=%" PRIx32 " ptem=%" PRIx32 " hash=" TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, vsid, ptem, hash); @@ -361,7 +360,7 @@ static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env, pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte); if (pte_offset == -1) { /* Secondary PTEG lookup */ - LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx " vsid=%" PRIx32 " api=%" PRIx32 " hash=" TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, vsid, ptem, ~hash); @@ -476,7 +475,8 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, return 1; } - LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); + qemu_log_mask(CPU_LOG_MMU, + "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); /* 7. Check access permissions */ @@ -484,7 +484,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, if (need_prot[rwx] & ~prot) { /* Access right violation */ - LOG_MMU("PTE access rejected\n"); + qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); if (rwx == 2) { cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; @@ -501,7 +501,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, return 1; } - LOG_MMU("PTE access granted !\n"); + qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); /* 8. Update PTE referenced and changed bits if necessary */ diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index c72198a..b0278c9 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -27,10 +27,8 @@ //#define DEBUG_SLB #ifdef DEBUG_MMU -# define LOG_MMU(...) qemu_log(__VA_ARGS__) # define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0) #else -# define LOG_MMU(...) do { } while (0) # define LOG_MMU_STATE(cpu) do { } while (0) #endif @@ -420,12 +418,14 @@ static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env, ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN); /* Page address translation */ - LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, + "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx " hash " TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, hash); /* Primary PTEG lookup */ - LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, + "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx " hash=" TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, vsid, ptem, hash); @@ -433,7 +433,8 @@ static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env, if (pte_offset == -1) { /* Secondary PTEG lookup */ - LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, + "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, vsid, ptem, ~hash); @@ -522,7 +523,8 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, } return 1; } - LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); + qemu_log_mask(CPU_LOG_MMU, + "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); /* 5. Check access permissions */ @@ -532,7 +534,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, if ((need_prot[rwx] & ~prot) != 0) { /* Access right violation */ - LOG_MMU("PTE access rejected\n"); + qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); if (rwx == 2) { cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; @@ -556,7 +558,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, return 1; } - LOG_MMU("PTE access granted !\n"); + qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); /* 6. Update PTE referenced and changed bits if necessary */ diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 4a34a73..660be7f 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -32,10 +32,8 @@ //#define FLUSH_ALL_TLBS #ifdef DEBUG_MMU -# define LOG_MMU(...) qemu_log(__VA_ARGS__) # define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0) #else -# define LOG_MMU(...) do { } while (0) # define LOG_MMU_STATE(cpu) do { } while (0) #endif @@ -176,10 +174,10 @@ static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0, ret = check_prot(ctx->prot, rw, type); if (ret == 0) { /* Access granted */ - LOG_MMU("PTE access granted !\n"); + qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); } else { /* Access right violation */ - LOG_MMU("PTE access rejected\n"); + qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); } } } @@ -480,8 +478,9 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, ctx->nx = sr & 0x10000000 ? 1 : 0; vsid = sr & 0x00FFFFFF; target_page_bits = TARGET_PAGE_BITS; - LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip=" - TARGET_FMT_lx " lr=" TARGET_FMT_lx + qemu_log_mask(CPU_LOG_MMU, + "Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx + " nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx " ir=%d dr=%d pr=%d %d t=%d\n", eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0, rw, type); @@ -489,14 +488,16 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, hash = vsid ^ pgidx; ctx->ptem = (vsid << 7) | (pgidx >> 10); - LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n", + qemu_log_mask(CPU_LOG_MMU, + "pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n", ctx->key, ds, ctx->nx, vsid); ret = -1; if (!ds) { /* Check if instruction fetch is allowed, if needed */ if (type != ACCESS_CODE || ctx->nx == 0) { /* Page address translation */ - LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx + " htab_mask " TARGET_FMT_plx " hash " TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, hash); ctx->hash[0] = hash; @@ -527,13 +528,13 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, } #endif } else { - LOG_MMU("No access allowed\n"); + qemu_log_mask(CPU_LOG_MMU, "No access allowed\n"); ret = -3; } } else { target_ulong sr; - LOG_MMU("direct store...\n"); + qemu_log_mask(CPU_LOG_MMU, "direct store...\n"); /* Direct-store segment : absolutely *BUGGY* for now */ /* Direct-store implies a 32-bit MMU. @@ -2037,7 +2038,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) { PowerPCCPU *cpu = ppc_env_get_cpu(env); - LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value); + qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value); assert(!env->external_htab); if (env->spr[SPR_SDR1] != value) { env->spr[SPR_SDR1] = value; @@ -2079,7 +2080,8 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) { PowerPCCPU *cpu = ppc_env_get_cpu(env); - LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, + qemu_log_mask(CPU_LOG_MMU, + "%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, (int)srnum, value, env->sr[srnum]); #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { diff --git a/target-s390x/helper.c b/target-s390x/helper.c index 96a4f22..5958343 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -461,8 +461,8 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, return 1; } - DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__, - (uint64_t)vaddr, (uint64_t)raddr, prot); + qemu_log_mask(CPU_LOG_MMU, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", + __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); tlb_set_page(cs, orig_vaddr, raddr, prot, mmu_idx, TARGET_PAGE_SIZE); diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c index 61afbcf..2a0c6f0 100644 --- a/target-sparc/mmu_helper.c +++ b/target-sparc/mmu_helper.c @@ -213,10 +213,9 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, address, rw, mmu_idx, &page_size); vaddr = address; if (error_code == 0) { -#ifdef DEBUG_MMU - printf("Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr " - TARGET_FMT_lx "\n", address, paddr, vaddr); -#endif + qemu_log_mask(CPU_LOG_MMU, + "Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr " + TARGET_FMT_lx "\n", address, paddr, vaddr); tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return 0; }