From patchwork Mon Nov 17 16:47:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 411728 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3F9061401EB for ; Tue, 18 Nov 2014 03:55:39 +1100 (AEDT) Received: from localhost ([::1]:48895 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPaT-0006Ok-IS for incoming@patchwork.ozlabs.org; Mon, 17 Nov 2014 11:55:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59953) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTh-0001lC-TD for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XqPTc-0007Dv-Kz for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:37 -0500 Received: from mail-pa0-f41.google.com ([209.85.220.41]:54399) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTc-0007Dn-Fc for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:32 -0500 Received: by mail-pa0-f41.google.com with SMTP id rd3so8009618pab.14 for ; Mon, 17 Nov 2014 08:48:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1TV55Jvu8yfrKO+1XrhAsg2wioFLrbsgrjuQvjhPCOg=; b=iPAK2YVSOcmMYZdEsTeT+Iza9f3qIu+CkehSCtndhjGxB1JFa/XU5ha4fXtvYFdc8o uuj0rVDdzdaKts1X1C1AmxJXjINVWvV+anrj/nhAAUCwmE8rYJUN2z3CbbyBp5NBFHPx M8wrzzPszuSqQltLZOlYtKlN0UMC+JNpkSgbTbM8YitnnGqqLd9VPPYiHhihtGOjPC+W rb9Ux9DUQpDghsOzS/lnB35zBFdA6rYn6QF6d8FJYhfZA0OxOZXDehocrEy+gwuhAhMq XfBUUl7JgxnRskhX1meTgIYQRWomzXMOWJ8dwPGCPABfNJH7D/DfxXUknl7UfI4724ap pGYw== X-Gm-Message-State: ALoCoQnnH6XgJkYenTWaVLMBwdIoy1PmIFtBUTMfcQPU0ippckenc5ssgv+kOUVaUa069bZAyAao X-Received: by 10.68.129.69 with SMTP id nu5mr30696867pbb.51.1416242911890; Mon, 17 Nov 2014 08:48:31 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r2sm18499056pdi.60.2014.11.17.08.48.30 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 17 Nov 2014 08:48:31 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Mon, 17 Nov 2014 10:47:47 -0600 Message-Id: <1416242878-876-16-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> References: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.41 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v11 15/26] target-arm: make CSSELR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Rename CSSELR (cache size selection register) and add secure instance (AArch32). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Replaced call to ARM_CP_SECSTATE_TEST with direct access v7 -> v8 - Fix CSSELR CP register definition to use .opc0 rather than .cp. v5 -> v6 - Changed _el field variants to be array based - Switch to use distinct CPREG secure flags. - Merged CSSELR and CSSELR_EL1 reginfo entries v4 -> v5 - Changed to use the CCSIDR cpreg bank flag to select the csselr bank instead of the A32_BANKED macro. This more accurately uses the secure state bank matching the CCSIDR. --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 14 +++++++++++--- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6559aa8..f06d209 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -177,7 +177,15 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; - uint64_t c0_cssel; /* Cache size selection. */ + union { /* Cache size selection */ + struct { + uint64_t _unused_csselr0; + uint64_t csselr_ns; + uint64_t _unused_csselr1; + uint64_t csselr_s; + }; + uint64_t csselr_el[4]; + }; union { /* System control register. */ struct { uint64_t _unused_sctlr; diff --git a/target-arm/helper.c b/target-arm/helper.c index d555fe4..05e66fb 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -776,7 +776,14 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = arm_env_get_cpu(env); - return cpu->ccsidr[env->cp15.c0_cssel]; + + /* Acquire the CSSELR index from the bank corresponding to the CCSIDR + * bank + */ + uint32_t index = A32_BANKED_REG_GET(env, csselr, + ri->secure & ARM_CP_SECSTATE_S); + + return cpu->ccsidr[index]; } static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -903,8 +910,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), - .writefn = csselr_write, .resetvalue = 0 }, + .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), + offsetof(CPUARMState, cp15.csselr_ns) } }, /* Auxiliary ID register: this actually has an IMPDEF value but for now * just RAZ for all cores: */